參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁(yè)數(shù)： 45/49頁(yè)
文件大小： 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
5
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
CLOCK
Chip_Select_N
STP
D[7:0]
NXT
3-State (input)
t
PWRDN
3-State (input)
3-State (ignored)
DIR
3-State
Figure 3. ULPI Behavior with Chip_Select_N as a Power-Down Control Signal
Power Down Using Chip_Select
When CHIP SELECT_N is de-asserted (HIGH), the
FUSB2805 three-states the ULPI interface pins and
powers
down
the
internal
circuitry.
If
CHIP
SELECT_N is not used as a power-down control
signal, it is tied to a LOW. Figure 3 shows the ULPI
interface
behavior
when
CHIP
SELECT_N
is
asserted and subsequently de-asserted.
After the tPWRDN duration, the CLOCK output enters
three-state and is ignored by the link.
Power-On Reset (POR)
The power supply for the internal regulators is VCC. This
supply is fed into the 3.3 V and 1.2 V regulators. The
output of the 3.3 V regulator is VCC3V3. The 1.2 V
regulator generates VDD1V2.
During the power-up stage, the POR is held in a stable
state to ensure that the digital logic does not operate
the I/O or any analog circuit in such a way that may be
damaging to the rest of the system.
The output of the POR block, PORB (internal signal),
should be 1b0 during the power supply ramping period.
Once the power supplies have completely ramped,
PORB should be de-asserted. This signal is driven into
the 19.2 / 26 MHz to 12 MHz PLL. The POR signal
(active HIGH reset) in the USB OTG PHY block must
remain asserted for no less than 40 s.
PORB de-assertion is determined via a comparator on
VCC3V3 with a POR trigger threshold, VPOR, of 2.0 V.
Figure 4 illustrates how PORB should be pulsed based
on the voltage level of VCC3V3. This diagram also shows
what the POR should do to PORB when VCC3V3 drops
below VPOR for any length of time.
When CLOCK starts toggling after power up, the USB
link controller must issue a reset command over the
ULPI bus to ensure correct operation.
PORB /
PLL
Reset
VCC3V3
VPOR
T0
T1
VCC3V3 = 3.3V
T1 = T0 + 40s
VPOR = 2.2V
T2
T3
T4
PHY POR
T4 = T3 + 40s
Figure 4. Power-On Reset Sequence
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