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參數(shù)資料
| 型號： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 10/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標(biāo)準包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
18
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Link Decision Times
The amount of clock cycles allocated to the link to respond to a received packet and correctly receive back-to-back
packets is given in Table 7.
Table 7.
Link Decision Times
Parameter Name
HS PHY
Delay
FS PHY
Delay
LS PHY
Delay
Definition
Transmit-Transmit
(Host Only)
15 to 24
7 to 18
77 to 247
Number of clocks a host link must wait before driving the
TXCMD for the second packet.
In HS, the link starts counting from the assertion of STP for
the first packet.
In FS, the link starts counting from the RXCMD indicating
LINESTATE has transitioned from SE0-to-J for the first
packet. The timings given ensure inter-packet delays of 2.0
to 6.5 bit times.
Receive-Transmit
(Host or Peripheral)
1 to 14
7 to 18
16 to 18
Number of clocks the link must wait before driving the
TXCMD for the transmit packet.
In HS, the link starts counting from the end of the receive
packet (de-assertion of DIR or an RXCMD indicating
RxActive is LOW).
In FS/LS, the link starts counting from the RXCMD
indicating LINESTATE has transitioned from SE0-to-J for
the receive packet. The timings given ensure inter-packet
delays of 2.0 to 6.5 bit times.
Receive-Receive
(Peripheral Only)
1
Minimum number of clocks between consecutive receive
packets. The link must be capable of receiving both
packets.
Transmit-Receive
(Host or Peripheral)
92
80
718
Host or peripheral transmits a packet, then times out after
this number of clock cycles if a response is not received.
Any subsequent transmission can occur after this time.
CLOCK
D0-D7
STP
DIR
NXT
D0
TXCMD
DN-1
DATA
turn
around
D1
RX End Delay
( 3 to 8 clocks)
DN-4
DN-3
DN-2
DN
EOP
DP or
DM
IDLE
SYNC
Link Decision Time (1 to 14 clocks)
TX Start Delay
(1 to 2 clocks)
USB Inter Packet Delay (8 to 192 HS bit times)
Figure 11.
HS Receive to Transmit Packet Timing, Example 1
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