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參數(shù)資料
| 型號： | FDMB668P |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 小信號晶體管 |
| 英文描述： | P-Channel 1.8V Logic Level PowerTrench MOSFET -20V, -6.1A, 35mohm |
| 中文描述： | 6.1 mA, 20 V, P-CHANNEL, Si, SMALL SIGNAL, MOSFET |
| 封裝： | ROHS COMPLIANT, 3 X 1.90 MM, 0.80 MM HEIGHT, MICROFET-8 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 436K |
| 代理商： | FDMB668P |
F
M
FDMB668P Rev.B
www.fairchildsemi.com
2
Electrical Characteristics
T
J
= 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
DSS
BV
DSS
T
J
I
DSS
I
GSS
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
I
D
= -250
μ
A, V
GS
= 0V
-20
V
I
D
= -250
μ
A, referenced to 25°C
-11.4
mV/°
C
V
DS
= -16V, V
GS
= 0V
V
GS
= ±8V, V
DS
= 0V
-1
μ
A
nA
±100
On Characteristics
V
GS(th)
V
GS(th)
T
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
V
GS
= V
DS
, I
D
= -250
μ
A
-0.4
-0.6
-1.0
V
I
D
= -250
μ
A, referenced to 25°C
2.8
mV/°C
r
DS(on)
Static Drain to Source On Resistance
V
GS
= -4.5V, I
D
= -6.1A
V
GS
= -2.5V, I
D
= -5.1A
V
GS
= -1.8V, I
D
= -4.3A
V
GS
= -4.5V, I
D
= -6.1A,T
J
= 125°C
V
DS
= -4.5V, I
D
= -6.1A
22
27
35
31
27
35
50
70
50
m
g
FS
Forward Transconductance
S
(Note 2)
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DS
= -10V, V
GS
= 0V,
f = 1MHz
1565
210
175
2085
280
265
pF
pF
pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
DD
= -10V, I
D
= -6.1A
V
GS
= -4.5V, R
GEN
= 6
7
9
14
18
282
135
59
31
ns
ns
ns
ns
nC
nC
nC
nC
176
84
42
22
3
5
V
GS
= 0V to -10V
V
GS
= 0V to -5V
V
DD
= -10V
I
D
= -6.1A
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
Notes:
1:
R
θ
JA
is the sum of the junction-to-case and case-to- ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the
drain pins.
R
θ
JC
is guaranteed by design while R
θ
JA
is determined by the user’s board design.
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
V
GS
= 0V, I
S
= -1.6A (Note 2)
-0.7
29
15
-1.2
44
23
V
ns
nC
I
F
= -6.1A, di/dt = 100A/
μ
s
2:
Pulse Test: Pulse Width < 300 us, Duty Cycle < 2%.
a)
65°C/W when mounted on a
1in
pad of 2 oz copper
b)
165°C/W when mounted on a
minimum pad .
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