
SMSC DS – FDC37N958FR
Rev. 09/01/99
GENERAL PURPOSE I/O (GPIO)....................................................................................................... 197
MULTIPLEXED PINS .......................................................................................................................... 203
REAL TIME CLOCK............................................................................................................................ 209
VCC1 POR........................................................................................................................................... 211
INTERNAL REGISTERS ..................................................................................................................... 212
TIME CALENDAR AND ALARM......................................................................................................... 213
UPDATE CYCLE ................................................................................................................................. 214
CONTROL AND STATUS REGISTERS.............................................................................................. 215
INTERRUPTS...................................................................................................................................... 220
FREQUENCY DIVIDER....................................................................................................................... 220
PERIODIC INTERRUPT SELECTION................................................................................................. 220
POWER MANAGEMENT..................................................................................................................... 221
ACCESS.BUS...................................................................................................................................... 222
BACKGROUND................................................................................................................................... 222
REGISTER DESCRIPTION ................................................................................................................. 223
PS/2 DEVICE INTERFACE.................................................................................................................. 229
PS/2 LOGIC OVERVIEW..................................................................................................................... 229
SERIAL INTERRUPTS........................................................................................................................ 233
FDC37N958FR CONFIGURATION ..................................................................................................... 238
CONFIGURATION ELEMENTS........................................................................................................... 238
TYPICAL SEQUENCE OF CONFIGURATION OPERATION.............................................................. 239
CONFIGURATION REGISTERS ......................................................................................................... 241
OPEN MODE REGISTERS.................................................................................................................. 266