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參數(shù)資料
| 型號(hào)： | FDC37N958FR |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Notebook I/O Controller with Enhanced Keyboard and System Control |
| 中文描述： | 筆記本電腦的I / O控制器，具有增強(qiáng)型鍵盤(pán)和系統(tǒng)控制 |
| 文件頁(yè)數(shù)： | 41/316頁(yè) |
| 文件大?。?/td> | 999K |
| 代理商： | FDC37N958FR |
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SMSC DS – FDC37N958FR
Page 35
Rev. 09/01/99
MAIN STATUS REGISTER
FDC I/O Base Address + 0x04 (READ ONLY)
The Main Status Register is a read-only register
and indicates the status of the disk controller. The
Main Status Register can be read at any time.
The MSR indicates when the disk controller is
ready to receive data via the Data Register. It
should be read before each byte transferring to or
from the data register except in DMA mode. No
delay is required when reading the MSR after a
data transfer.
7
6
5
4
3
2
1
0
RQM
DIO
NON
DMA
CMD
BUSY
DRV3
BUSY
DRV2
BUSY
DRV1
BUSY
DRV0
BUSY
BIT 0 - 3 DRVx BUSY
These bits are set to 1s when a drive is in the
seek portion of a command, including implied and
overlapped seeks and recalibrates.
BIT 4 COMMAND BUSY
This bit is set to a “1” when a command is in
progress. This bit will go active after the
command byte has been accepted and goes
inactive at the end of the results phase. If there is
no result phase (Seek, Recalibrate commands),
this bit is returned to a “0” after the last command
byte.
BIT 5 NON-DMA
This mode is selected in the SPECIFY command
and will be set to a “1” during the execution phase
of a command. This is for polled data transfers
and helps differentiate between the data transfer
phase and the reading of result bytes.
BIT 6 DIO
Indicates the direction of a data transfer once a
RQM is set. A “1” indicates a read and a “0”
indicates a write is required.
BIT 7 RQM
Indicates that the host can transfer data if set to a
“1”. No access is permitted if set to a “0”.
DATA REGISTER (FIFO)
FDC I/O Base Address + 0x05 (READ/WRITE)
All command parameter information, disk data
and result status are transferred between the host
processor and the FDC through the Data
Register. Data transfers are governed by the
RQM and DIO bits in the Main Status Register.
The Data Register defaults to FIFO disabled
mode after any form of reset. This maintains
PC/AT hardware compatibility. The default values
can be changed through the Configure command
(enable full FIFO operation with threshold control).
The advantage of the FIFO is that it allows the
system a larger DMA latency without causing a
disk error. Table 19 gives several examples of
the delays with a FIFO. The data is based upon
the following formula:
Threshold # x [8/DATA RATE] - 1.5ms = Delay
At the start of a command, the FIFO action is
always disabled and command parameters must
be sent based upon the RQM and DIO bit
settings. As the command execution phase is
entered, the FIFO is cleared of any data to ensure
that invalid data is not transferred.
An overrun or underrun will terminate the current
command and the transfer of data. Disk writes will
complete the current sector by generating a 00
pattern and valid CRC. Reads require the host to
remove the remaining data so that the result
phase may be entered.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FDC37N958FR-PQFP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral (Multifunction) Controller |
| FDC37N958FRTQFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
| FDC37N971TQFP WAF | 制造商:SMSC 功能描述: |
| FDC37N972 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Advanced Notebook I/O Controller with Enhanced Keyboard Control and System Management |
| FDC37N972FBGA | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述: |
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