參數(shù)資料
型號(hào)： FDC37N958FR
廠商： Electronic Theatre Controls, Inc.
英文描述： Notebook I/O Controller with Enhanced Keyboard and System Control
中文描述： 筆記本電腦的I / O控制器，具有增強(qiáng)型鍵盤(pán)和系統(tǒng)控制
文件頁(yè)數(shù)： 122/316頁(yè)
文件大?。?/td> 999K
代理商： FDC37N958FR
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SMSC DS – FDC37N958FR
Page 116
Rev. 09/01/99
DEVICE CONTROL REGISTER (dcr)
ADDRESS OFFSET = 02H
The Control Register is located at an offset of
'02H' from the base address. The Control
Register is initialized to zero by the RESET input,
bits 0 to 5 only being affected; bits 6 and 7 are
hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the nSTROBE
output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the nAUTOFD
output. A logic “1” causes the printer to generate
a line feed after each line is printed. A logic “0”
means no autofeed.
BIT 2 nINIT - nINITIATE OUTPUT
This bit is output onto the nINIT output without
inversion.
BIT 3 SELECTIN
This bit is inverted and output onto the nSLCTIN
output. A logic “1” on this bit selects the printer; a
logic “0” means the printer is not selected.
BIT 4 ackIntEn - INTERRUPT REQUEST
ENABLE
The interrupt request enable bit when set to a high
level may be used to enable interrupt requests
from the Parallel Port to the CPU due to a low to
high transition on the nACK input. Refer to the
description of the interrupt under Operation,
Interrupts.
BIT 5 DIRECTION
If mode=000 or mode=010, this bit has no effect
and the direction is always out regardless of the
state of this bit. In all other modes, Direction is
valid and a logic 0 means that the printer port is in
output mode (write); a logic “1” means that the
printer port is in input mode (read).
BITS 6 and 7
during a read are a low level, and
cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this
FIFO are transmitted by a hardware handshake to
the peripheral using the standard parallel port
protocol. Transfers to the FIFO are byte aligned.
This mode is only defined for the forward
direction.
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this
FIFO, when the direction bit is “0”, are transmitted
by a hardware handshake to the peripheral using
the ECP parallel port protocol. Transfers to the
FIFO are byte aligned.
Data bytes from the peripheral are read under
automatic hardware handshake from ECP into this
FIFO when the direction bit is “1”. Reads or
DMAs from the FIFO will return bytes of ECP data
to the system.
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or
from the system to this FIFO in any direction. Data
in the tFIFO will not be transmitted to the to the
parallel port lines using a hardware protocol
handshake. However, data in the tFIFO may be
displayed on the parallel port data lines.
The tFIFO will not stall when overwritten or
underrun. If an attempt is made to write data to a
full tFIFO, the new data is not accepted into the
tFIFO. If an attempt is made to read data from an
empty tFIFO, the last data byte is re-read again.
The full and empty bits must always keep track of
the correct FIFO state. The tFIFO will transfer
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參數(shù)描述
FDC37N958FR-PQFP 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Peripheral (Multifunction) Controller
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FDC37N971TQFP WAF 制造商:SMSC 功能描述:
FDC37N972 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:Advanced Notebook I/O Controller with Enhanced Keyboard Control and System Management
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