參數(shù)資料
型號(hào)： FDC37N958FR
廠商： Electronic Theatre Controls, Inc.
英文描述： Notebook I/O Controller with Enhanced Keyboard and System Control
中文描述： 筆記本電腦的I / O控制器，具有增強(qiáng)型鍵盤和系統(tǒng)控制
文件頁(yè)數(shù)： 235/316頁(yè)
文件大小： 999K
代理商： FDC37N958FR
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SMSC DS – FDC37N958FR
Page 229
Rev. 09/01/99
PS/2 Device Interface
PS/2 Logic Overview
The FDC37N958FR has four PS/2 serial ports
implemented in hardware which are directly
controlled by the on chip 8051. The hardware
implementation eliminates the need to bit bang
I/O ports to generate PS/2 ports. The PS/2 logic
allows the host to communicate to any serial
auxiliary devices compatible with the PS/2
interface through any one of four ports : EM, KB,
IM and PS2. There are two identical PS/2
channels, each containing a set of five operating
registers. Channel 1 (PS/2 Port 1) consists of
ports EM and KB and channel 2 (PS/2 Port 2)
consists of ports IM and PS2.
Each of the four PS/2 serial ports use a
synchronous serial protocol to communicate with
the auxiliary device. Each PS/2 port has two
signal lines : Clock and Data. Both signal lines
are bi-directional and imply open drain outputs.
A pull-up resistor (typically 3.3K) is connected to
the clock and data lines. This allows either the
FDC37N958FR PS/2 logic or the auxiliary device
to control both lines. Regardless, the auxiliary
device provides the clock for transmit and
receive operations. The serial packet is made
up of eleven bits, listed in order as they will
appear on the data line : start bit, eight data bits
(least significant bit first), odd parity, and stop
bit. Each bit cell is from 60
"
S to 100
"
S long.
The data is latched on the high to low transition
of the clock.
Transmitting to the Remote Auxiliary Device
The PS/2 serial protocol requires that the
auxiliary device respond to all transmissions that
it receives. The response will either be an 0XFA
or 0xEE. The response is stored in the PS/2
ports Receive register. Thus, after each
transmission the Receive register should contain
either 0xFA or 0xEE.
Note:
programmers details.
Refer to Application Note 6.19 for
Receiving from the Remote Auxiliary Device
A port is set to receive by selecting the port and
enabling the receiver. This is done by writing to
the CONTROL register. The PS/2 logic floats
the PS/2 port’s clock and data line when the port
is selected to receive. The auxiliary device
initiates the transfer by driving the data line low
and 12
"
S later driving the clock low. The
FDC37N958FR PS/2 Logic recognizes this as a
start bit. The auxiliary device proceeds by
transmitting ten more bits to the FDC37N958FR.
The PS/2 Logic latches the data on the high to
low transition of the clock. After the stop bit, the
PS/2 Logic drives the clock line low until the
Receive register is read by the 8051. If there is
no error in the transfer, the PS/2 logic sets the
Ready bit of the Status register, clears the Error
bit of Status register, and clears the Error
register. If, however, the receive operation does
not complete in 2 ms, the Error bit of the Status
register is set together with the RECTIMOUT bit
of the Error register, and the Ready bit is not set.
Note:
programmers details.
Refer to Application Note 6.19 for
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