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參數(shù)資料
| 型號： | FDC37C665IR |
| 廠商： | SMSC Corporation |
| 英文描述： | 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support |
| 中文描述： | 3 / 5伏先進的高性能多模并口超級I / O軟盤與Infranred支持磁盤控制器 |
| 文件頁數(shù)： | 75/162頁 |
| 文件大小： | 562K |
| 代理商： | FDC37C665IR |
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75
SERIAL PORT
(UART)
The FDC37C665IR incorporates two full function
UARTs. They are compatible with the
NS16450, the 16450 ACE registers and the
NS16550A. The UARTS perform serial-to-
parallel conversion on received characters and
parallel-to-serial
conversion
characters. The data rates are independently
programmable from 115.2K baud down to 50
baud. The character options are programmable
for 1 start; 1, 1.5 or 2 stop bits; even, odd, sticky
or no parity; and prioritized interrupts. The
UARTs each contain a programmable baud rate
generator that is capable of dividing the input
clock or crystal by a number from 1 to 65535.
The UARTs are also capable of supporting the
MIDI data rate. Refer to the FDC37C665IR
Configuration Registers.
on
transmit
Configuration description for information on
disabling, power down and changing the base
address of the UARTs. The interrupt from a
UART is enabled by programming OUT2 of that
UART to a logic "1". OUT2 being a logic "0"
disables that UART's interrupt.
REGISTER DESCRIPTION
Addressing of the accessible registers of the
Serial Port is shown below. The base
addresses of the serial ports are defined by the
configuration
registers
section). The Serial Port registers are located at
sequentially increasing addresses above these
base addresses. The FDC37C665IR/666IR
contains two serial ports, each of which contain
a register set as described below.
(see
Configuration
Table 33 - Addressing the Serial Port
A1
A0
0
0
Receive Buffer (read)
0
0
Transmit Buffer (write)
0
1
Interrupt Enable (read/write)
1
0
Interrupt Identification (read)
1
0
FIFO Control (write)
1
1
Line Control (read/write)
0
0
Modem Control (read/write)
0
1
Line Status (read/write)
1
0
Modem Status (read/write)
1
1
Scratchpad (read/write)
0
0
Divisor LSB (read/write)
0
1
Divisor MSB (read/write
DLAB*
0
0
0
X
X
X
X
X
X
X
1
1
A2
0
0
0
0
0
0
1
1
1
1
0
0
REGISTER NAME
*NOTE: DLAB is Bit 7 of the Line Control Register
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