參數(shù)資料
型號(hào): FDC37C665IR
廠商: SMSC Corporation
英文描述: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
中文描述: 3 / 5伏先進(jìn)的高性能多模并口超級(jí)I / O軟盤與Infranred支持磁盤控制器
文件頁數(shù): 116/162頁
文件大?。?/td> 562K
代理商: FDC37C665IR
116
INTEGRATED DRIVE ELECTRONICS INTERFACE
The IDE interface enables hard disks with
embedded controllers (AT and XT) to be
interfaced to the host processor. The following
definitions are for reference only. These
registers
are
not
FDC37C665IR. Access to these registers is
controlled by the FDC37C665IR. For more
information, refer to the IDE pin descriptions
and the ATA specification.
implemented
in
the
HOST FILE REGISTERS
The HOST FILE REGISTERS are accessed by
the AT Host, rather than the Local Processor.
There are two groups of registers, the AT Task
File, and the Miscellaneous AT Registers.
ADDRESS 1F0H-1F7H; 170H-177H
These AT registers contain the Task File
Registers. These registers communicate data,
command, and status information with the AT
host, and are addressed when nHDCS0 is low.
ADDRESS 376H/3F6H; 377H/3F7H
These AT registers may be used by the BIOS for
drive control. They are accessed by the AT
interface when nHDSC1 is active.
Figure 3 shows the AT Host Register Map of the
FDC37C665IR.
FIGURE 3 - HOST PROCESSOR REGISTER ADDRESS MAP (AT MODE)
PRIMARY
SECONDARY
1F0H
|
1F7H
177H
3F6H
|
3F7H
377H
170H
|
TASK FILE REGISTERS
376H
|
MISC. AT REGISTERS
TASK FILE REGISTERS
Task File Registers may be accessed by the
host AT when pin nHDCS0 is active (low). The
Data Register (1F0H) is 16 bits wide; the
remaining task file registers are 8 bits wide. The
task file registers are ATA and EATA
compatible. Please refer to the ATA and EATA
specifications. These are available from:
Global Engineering
2805 McGaw Street
Irvine, CA 92714
(800) 854-7179
(714) 261-1455
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參數(shù)描述
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