參數(shù)資料
型號(hào)： FDC37C665IR
廠商： SMSC Corporation
英文描述： 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
中文描述： 3 / 5伏先進(jìn)的高性能多模并口超級(jí)I / O軟盤(pán)與Infranred支持磁盤(pán)控制器
文件頁(yè)數(shù)： 40/162頁(yè)
文件大小： 562K
代理商： FDC37C665IR
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Table 19- Status Register 3
NAME
Unused. This bit is always "0".
Write
Protected
Unused. This bit is always "1".
Track 0
Indicates the status of the TRK0 pin.
Unused. This bit is always "1".
Head
Address
Drive Select
Indicates the status of the DS1, DS0 pins.
BIT NO.
7
6
SYMBOL
DESCRIPTION
WP
Indicates the status of the WP pin.
5
4
3
2
T0
HD
Indicates the status of the HDSEL pin.
1,0
DS1,0
RESET
There are three sources of system reset on the
FDC: the RESET pin of the FDC37C665IR, a
reset generated via a bit in the DOR, and a reset
generated via a bit in the DSR. At power on, a
Power On Reset initializes the FDC. All resets
take the FDC out of the power down state.
All operations are terminated upon a RESET,
and the FDC enters an idle state. A reset while
a disk write is in progress will corrupt the data
and CRC.
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the FDC waits for a
new command. Drive polling will start unless
disabled by a new Configure command.
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all
registers except those programmed by the
Specify command. The DOR reset bit is
enabled and must be cleared by the host to exit
the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same.
Both will reset the FDC core, which affects drive
status information and the FIFO circuits. The
DSR reset clears itself automatically while the
DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset.
The DOR reset is set automatically upon a pin
reset. The user must manually clear this reset
bit in the DOR to exit the reset state.
MODES OF OPERATION
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of the IDENT and
MFM bits 6 and 5 respectively of configuration
register 3.
PC/AT mode
- (IDENT high, MFM a "don't
care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (FINTR
and DRQ can be hi Z), and TC and DENSEL
become active high signals.
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參數(shù)描述
FDC37C665IRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
FDC37C666GT 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C669 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669_07 制造商:SMSC 制造商全稱(chēng):SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
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