參數(shù)資料
型號： FDC37C665IR
廠商： SMSC Corporation
英文描述： 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
中文描述： 3 / 5伏先進的高性能多模并口超級I / O軟盤與Infranred支持磁盤控制器
文件頁數(shù)： 104/162頁
文件大?。?/td> 562K
代理商： FDC37C665IR
104
Data bytes are always read from the head of
tFIFO regardless of the value of the direction bit.
For example if 44h, 33h, 22h is written to the
FIFO, then reading the tFIFO will return 44h,
33h, 22h in the same order as was written.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read,
10H is returned. This indicates to the system
that this is an 8-bit implementation. (PWord = 1
byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 7 compress
This bit is read only. During a read it is a low
level. This means that this chip does not
support hardware RLE compression. It does
support hardware de-compression!
BIT 6 intrValue
Returns the value on the ISA iRq line to
determine possible conflicts.
BITS 5:0 Reserved
During a read are a low level. These bits cannot
be written.
ecr (Extended Control Register)
ADDRESS OFFSET = 402H
Mode = all
This register controls the extended ECP parallel
port functions.
BITS 7,6,5
These bits are Read/Write and select the Mode.
BIT 4 nErrIntrEn
Read/Write (Valid only in ECP Mode)
1:Disables the interrupt generated on the
asserting edge of nFault.
0:
Enables an interrupt pulse on the high to
low edge of nFault. Note that an interrupt
will be generated if nFault is asserted
(interrupting) and this bit is written from a 1
to a 0. This prevents interrupts from being
lost in the time between the read of the ecr
and the write of the ecr.
BIT 3 dmaEn
Read/Write
1:
Enables DMA (DMA starts when serviceIntr
is 0).
0:
Disables DMA unconditionally.
BIT 2 serviceIntr
Read/Write
1:
Disables DMA and all of the service
interrupts.
0:
Enables one of the following 3 cases of
interrupts. Once one of the 3 service
interrupts has occurred serviceIntr bit shall
be set to a 1 by hardware, it must be reset
to 0 to re-enable the interrupts. Writing this
bit to a 1 will not cause an interrupt.
case dmaEn=1:
During DMA (this bit is set to a 1 when
terminal count is reached).
case dmaEn=0 direction=0:
This bit shall be set to 1 whenever there are
writeIntrThreshold or more bytes free in the
FIFO.
case dmaEn=0 direction=1:
This bit shall be set to 1 whenever there are
readIntrThreshold or more valid bytes to be
read from the FIFO.
BIT 1 full
Read only
1:
The FIFO cannot accept another byte or the
FIFO is completely full.
0:
The FIFO has at least 1 free byte.
BIT 0 empty
Read only
1:
The FIFO is completely empty.
0:
The FIFO contains at least 1 byte of data.
相關(guān)PDF資料
PDF描述
FDC37C665GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C666GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C67X ENHANCED SUPER I/O CONTROLLER WITH FAST IR
FDC37C957FR ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS
FDC37M600 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FDC37C665IRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
FDC37C666GT 制造商:SMSC 制造商全稱:SMSC 功能描述:High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C669 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669_07 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669FRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk
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