參數(shù)資料
型號(hào)： FDC37C665IR
廠商： SMSC Corporation
英文描述： 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
中文描述： 3 / 5伏先進(jìn)的高性能多模并口超級(jí)I / O軟盤與Infranred支持磁盤控制器
文件頁數(shù)： 108/162頁
文件大?。?/td> 562K
代理商： FDC37C665IR
108
are always possible with standard or PS/2
mode using program control of the control
signals.
Interrupts
The interrupts are enabled by
serviceIntr
in the
ecr
register.
serviceIntr
= 1 Disables the DMA and all of the
service interrupts.
serviceIntr
= 0Enables the selected interrupt
condition. If the interrupting
condition is valid, then the
interrupt
immediately when this bit is
changed from a 1 to a 0. This
can occur during Programmed
I/O if the number of bytes
removed or added from/to the
FIFO does not cross the
threshold.
is
generated
The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing. After a brief pulse low
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
An interrupt is generated when:
1.For DMA transfers: When
serviceIntr
is 0,
dmaEn is 1 and the DMA TC is received.
2.For Programmed I/O:
a. When
serviceIntr
is 0, dmaEn is 0,
direction
is
writeIntrThreshold or more free bytes in
the FIFO. Also, an interrupt is
generated when
serviceIntr
is cleared
to
0
whenever
writeIntrThreshold or more free bytes in
the FIFO.
0
and
there
are
there
are
b.
(1)When
serviceIntr
is 0, dmaEn is 0,
direction is 1 and there are
readIntrThreshold
bytes in the FIFO. Also, an
interrupt is generated when
serviceIntr
is cleared to 0
whenever
readIntrThreshold
bytes in the FIFO.
or
more
there
are
or
more
3. When nErrIntrEn is 0 and nFault transitions
from high to low or when nErrIntrEn is set
from 1 to 0 and nFault is asserted.
4. When ackIntEn is 1 and the nAck signal
transitions from a low to a high.
FIFO Operation
The FIFO threshold is set in the chip
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode. The FIFO is used by
selecting the Parallel Port FIFO mode or ECP
Parallel Port Mode. (FIFO test mode will be
addressed separately.) After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of
the FIFO flow control. In these descriptions,
<threshold> ranges from 1 to 16. The
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system.
相關(guān)PDF資料
PDF描述
FDC37C665GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C666GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C67X ENHANCED SUPER I/O CONTROLLER WITH FAST IR
FDC37C957FR ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS
FDC37M600 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FDC37C665IRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
FDC37C666GT 制造商:SMSC 制造商全稱:SMSC 功能描述:High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C669 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669_07 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669FRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk
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