參數(shù)資料
型號(hào)： FDC37C665IR
廠商： SMSC Corporation
英文描述： 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
中文描述： 3 / 5伏先進(jìn)的高性能多模并口超級(jí)I / O軟盤與Infranred支持磁盤控制器
文件頁(yè)數(shù)： 42/162頁(yè)
文件大小： 562K
代理商： FDC37C665IR
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)當(dāng)前第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)
42
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host reads (writes)
from (to) the FIFO until empty (full), then the
transfer request goes inactive. The host must
be very responsive to the service request. This
is the desired case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
Non-DMA Mode - Transfers from the FIFO to
the Host
The FINT pin and RQM bits in the Main Status
Register are activated when the FIFO contains
(16-<threshold>) bytes or the last bytes of a full
sector have been placed in the FIFO. The FINT
pin can be used for interrupt-driven systems,
and RQM can be used for polled systems. The
host must respond to the request by reading
data from the FIFO. This process is repeated
until the last byte is transferred out of the FIFO.
The FDC will deactivate the FINT pin and RQM
bit when the FIFO becomes empty.
Non-DMA Mode - Transfers from the Host to the
FIFO
The FINT pin and RQM bit in the Main Status
Register are activated upon entering the
execution phase of data transfer commands.
The host must respond to the request by writing
data into the FIFO. The FINT pin and RQM bit
remain true until the FIFO becomes full. They
are set true again when the FIFO has
<threshold> bytes remaining in the FIFO. The
FINT pin will also be deactivated if TC and
nDACK both go inactive. The FDC enters the
result phase after the last byte is taken by the
FDC from the FIFO (i.e. FIFO empty condition).
DMA Mode - Transfers from the FIFO to the
Host
The FDC activates the DDRQ pin when the
FIFO contains (16 - <threshold>) bytes, or the
last byte of a full sector transfer has been
placed in the FIFO. The DMA controller must
respond to the request by reading data from the
FIFO. The FDC will deactivate the DDRQ pin
when the FIFO becomes empty. FDRQ goes
inactive after nDACK goes active for the last
byte of a data transfer (or on the active edge of
nIOR, on the last byte, if no edge is present on
nDACK). A data underrun may occur if FDRQ
is not removed in time to prevent an unwanted
cycle.
DMA Mode - Transfers from the Host to the
FIFO
The FDC activates the FDRQ pin when entering
the execution phase of the data transfer
commands. The DMA controller must respond
by activating the nDACK and nIOW pins and
placing data in the FIFO. FDRQ remains active
until the FIFO becomes full. FDRQ is again set
true when the FIFO has <threshold> bytes
remaining in the FIFO. The FDC will also
deactivate the FDRQ pin when TC becomes true
(qualified by nDACK), indicating that no more
data is required. FDRQ goes inactive after
nDACK goes active for the last byte of a data
transfer (or on the active edge of nIOW of the
last byte, if no edge is present on nDACK). A
data overrun may occur if FDRQ is not removed
in time to prevent an unwanted cycle.
Data Transfer Termination
The FDC supports terminal count explicitly
through the TC pin and implicitly through the
underrun/overrun
and
functions. For full sector transfers, the EOT
parameter can define the last sector to be
transferred in a single or multi-sector transfer.
end-of-track
(EOT)
相關(guān)PDF資料
PDF描述
FDC37C665GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C666GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C67X ENHANCED SUPER I/O CONTROLLER WITH FAST IR
FDC37C957FR ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS
FDC37M600 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FDC37C665IRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
FDC37C666GT 制造商:SMSC 制造商全稱:SMSC 功能描述:High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C669 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669_07 制造商:SMSC 制造商全稱:SMSC 功能描述:PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support
FDC37C669FRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*