參數(shù)資料
型號： FDC37C665GT
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 存儲(chǔ)控制器/管理單元
英文描述： High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述： 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝： QFP-100
文件頁數(shù)： 96/162頁
文件大?。?/td> 562K
代理商： FDC37C665GT
96
EPP 1.7 Write
The timing for a write operation (address or
data) is shown in timing diagram EPP 1.7 Write
Data or Address cycle. IOCHRDY is driven
active low when nWAIT is active low during the
EPP cycle. This can be used to extend the cycle
time. The write cycle can complete when
nWAIT is inactive high.
Write Sequence of Operation
1.The host sets PDIR bit in the control register
to a logic "0". This asserts nWRITE.
2.The host selects an EPP register, places data
on the SData bus and drives nIOW active.
3.The chip places address or data on PData
bus.
4.Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
5.If nWAIT is asserted, IOCHRDY is deasserted
until the peripheral deasserts nWAIT or a
time-out occurs.
6. When the host deasserts nI0W the chip
deasserts nDATASTB or nADDRSTRB and
latches the data from the SData bus for the
PData bus.
7.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
EPP 1.7 Read
The timing for a read operation (data) is shown
in timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be
used to extend the cycle time. The read cycle
can complete when nWAIT is inactive high.
Read Sequence of Operation
1.
The host sets PDIR bit in the control
register to a logic "1". This deasserts
nWRITE and tri-states the PData bus.
The host selects an EPP register and drives
nIOR active.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
If nWAIT is asserted, IOCHRDY is
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
The Peripheral drives PData bus valid.
The Peripheral deasserts nWAIT, indicating
that PData is valid and the chip may begin
the termination phase of the cycle.
7. When the host deasserts nI0R the chip
deasserts nDATASTB or nADDRSTRB.
8.
Peripheral tri-states the PData bus.
9.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
2.
3.
4.
5.
6.
相關(guān)PDF資料
PDF描述
FDC37C666GT High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C67X ENHANCED SUPER I/O CONTROLLER WITH FAST IR
FDC37C957FR ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS
FDC37M600 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
FDC37M601 ENHANCED SUPER I/O CONTROLLER WITH INFRARED SUPPORT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FDC37C665GT_07 制造商:SMSC 制造商全稱:SMSC 功能描述:High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
FDC37C665GT-MS 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller- Pb Free RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
FDC37C665GTQFP 功能描述:輸入/輸出控制器接口集成電路 Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
FDC37C665IR 制造商:SMSC 制造商全稱:SMSC 功能描述:3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
FDC37C665IRQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:SMSC 功能描述:
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