參數(shù)資料
型號: FDC37C665GT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 存儲控制器/管理單元
英文描述: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述: 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 125/162頁
文件大?。?/td> 562K
代理商: FDC37C665GT
125
CR2
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 02H. The default
value of this register after power up is DCH.
Table 51 - CR2
BIT NO.
0,1
BIT NAME
UART 1 Address
Select
DESCRIPTION
These bits select the Primary Serial Port Address.
1 0 COM Port ADDRESS
0 0 COM1 3F8H (Default)
0 1 COM2 2F8H
1 0 COM3 (Refer to CR1, bits 5,6)
1 1 COM4 (Refer to CR1, bits 5,6)
A high level on this bit, enables the Primary Serial Port (Default).
A low level on this bit disables the Primary Serial Port.
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
These bits select the Secondary Serial Port Address.
5 4 COM Port ADDRESS
0 0 COM1 3F8H
0 1 COM2 2F8H (Default)
1 0 COM3 (Refer to CR1, bits 5,6)
1 1 COM4 (Refer to CR1, bits 5,6)
A high level on this bit enables the Secondary Serial Port
(Default). A low level on this bit disables the Secondary Serial
Port.
A high level on this bit, allows normal operation of the Secondary
Serial Port (Default). A low level on this bit places the Secondary
Serial Port into Power Down Mode.
2
UART 1 Enable
3
UART 1 Power
down
4,5
UART 2 Address
Select
6
UART 2 Enable
7
UART 2 Power
down
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