參數(shù)資料
型號: FDC37C665GT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 存儲控制器/管理單元
英文描述: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述: 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 86/162頁
文件大?。?/td> 562K
代理商: FDC37C665GT
86
Table 37 - Register Summary for an Individual UART Channel
REGISTER
ADDRESS*
REGISTER NAME
REGISTER
SYMBOL
BIT 0
BIT 1
ADDR = 0
DLAB = 0
Receive Buffer Register (Read Only)
RBR
Data Bit 0
(Note 1)
Data Bit 1
ADDR = 0
DLAB = 0
Transmitter Holding Register (Write Only)
THR
Data Bit 0
Data Bit 1
ADDR = 1
DLAB = 0
Interrupt Enable Register
IER
Enable
Received Data
Available
Interrupt
(ERDAI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
ADDR = 2
Interrupt Ident. Register (Read Only)
IIR
"0" if Interrupt
Pending
Interrupt ID Bit
ADDR = 2
FIFO Control Register (Write Only)
FCR
FIFO Enable
RCVR FIFO
Reset
ADDR = 3
Line Control Register
LCR
Word Length
Select Bit 0
(WLS0)
Word Length
Select Bit 1
(WLS1)
ADDR = 4
MODEM Control Register
MCR
Data Terminal
Ready (DTR)
Data Ready
(DR)
Request to
Send (RTS)
ADDR = 5
Line Status Register
LSR
Overrun Error
(OE)
ADDR = 6
MODEM Status Register
MSR
Delta Clear to
Send (DCTS)
Delta Data Set
Ready
(DDSR)
ADDR = 7
Scratch Register (Note 4)
SCR
Bit 0
Bit 1
ADDR = 0
DLAB = 1
Divisor Latch (LS)
DDL
Bit 0
Bit 1
ADDR = 1
DLAB = 1
Divisor Latch (MS)
DLM
Bit 8
Bit 9
*DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Note 1: Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
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相關代理商/技術參數(shù)
參數(shù)描述
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