參數(shù)資料
型號(hào): FDC37C665GT
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 存儲(chǔ)控制器/管理單元
英文描述: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
中文描述: 1 Mbps, IDE COMPATIBLE, FLOPPY DISK DRIVE CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 87/162頁
文件大小: 562K
代理商: FDC37C665GT
87
Table 37 - Register Summary for an Individual UART Channel (continued)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 2
Data Bit 3
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 7
0
Enable Receiver
Line Status
Interrupt (ELSI)
Enable MODEM
Status Interrupt
(EMSI)
0
0
0
Interrupt ID Bit
Interrupt ID Bit
(Note 5)
0
0
FIFOs Enabled
(Note 5)
FIFOs Enabled
(Note 5)
XMIT FIFO
Reset
DMA Mode
Select (Note 6)
Reserved
Reserved
RCVR Trigger
LSB
RCVR Trigger
MSB
Divisor Latch
Access Bit
(DLAB)
Number of Stop
Bits (STB)
Parity Enable
(PEN)
Even Parity
Select (EPS)
Stick Parity
Set Break
OUT1
(Note 3)
OUT2
(Note 3)
Loop
0
0
0
Parity Error (PE)
Framing Error
(FE)
Break Interrupt
(BI)
Transmitter
Holding Register
(THRE)
Transmitter
Empty (TEMT)
(Note 2)
Error in RCVR
FIFO (Note 5)
Trailing Edge
Ring Indicator
(TERI)
Bit 2
Delta Data
Carrier Detect
(DDCD)
Clear to Send
(CTS)
Data Set Ready
(DSR)
Ring Indicator
(RI)
Data Carrier
Detect (DCD)
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
Note 3: This bit no longer has a pin associated with it.
Note 4: When operating in the XT mode, this register is not available.
Note 5: These bits are always zero in the non-FIFO mode.
Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip.
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