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參數(shù)資料
| 型號： | FDC37B72X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O Controller with ACPI Support |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 99/244頁 |
| 文件大?。?/td> | 1037K |
| 代理商： | FDC37B72X |
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99
BITS 6 and 7
during a read are a low level, and
cannot be written.
cFifo (Parallel Port Data FIFO)
ADDRESS OFFSET = 400h
Mode = 010
Bytes written or DMAed from the system to this
FIFO are transmitted by a hardware handshake
to the peripheral using the standard parallel port
protocol. Transfers to the FIFO are byte
aligned. This mode is only defined for the
forward direction.
ecpDFifo (ECP Data FIFO)
ADDRESS OFFSET = 400H
Mode = 011
Bytes written or DMAed from the system to this
FIFO, when the direction bit is 0, are transmitted
by a hardware handshake to the peripheral
using the ECP parallel port protocol. Transfers
to the FIFO are byte aligned.
Data bytes from the peripheral are read under
automatic hardware handshake from ECP into
this FIFO when the direction bit is 1. Reads or
DMAs from the FIFO will return bytes of ECP
data to the system.
tFifo (Test FIFO Mode)
ADDRESS OFFSET = 400H
Mode = 110
Data bytes may be read, written or DMAed to or
from the system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the
to the parallel port lines using a hardware
protocol handshake. However, data in the
tFIFO may be displayed on the parallel port data
lines.
The tFIFO will not stall when overwritten or
underrun. If an attempt is made to write data to
a full tFIFO, the new data is not accepted into
the tFIFO. If an attempt is made to read data
from an empty tFIFO, the last data byte is re-
read again. The full and empty bits must
always keep track of the correct FIFO state. The
tFIFO will transfer data at the maximum ISA
rate so that software may generate performance
metrics.
The FIFO size and interrupt threshold can be
determined by writing bytes to the FIFO and
checking the full and serviceIntr bits.
The writeIntrThreshold can be determined by
starting with a full tFIFO, setting the direction bit
to 0 and emptying it a byte at a time until
serviceIntr is set. This may generate a spurious
interrupt, but will indicate that the threshold has
been reached.
The readIntrThreshold can be determined by
setting the direction bit to 1 and filling the empty
tFIFO a byte at a time until serviceIntr is set.
This may generate a spurious interrupt, but will
indicate that the threshold has been reached.
Data bytes are always read from the head of
tFIFO regardless of the value of the direction bit.
For example if 44h, 33h, 22h is written to the
FIFO, then reading the tFIFO will return 44h,
33h, 22h in the same order as was written.
cnfgA (Configuration Register A)
ADDRESS OFFSET = 400H
Mode = 111
This register is a read only register. When read,
10H is returned. This indicates to the system
that this is an 8-bit implementation. (PWord = 1
byte)
cnfgB (Configuration Register B)
ADDRESS OFFSET = 401H
Mode = 111
BIT 7 compress
This bit is read only. During a read it is a low
level. This means that this chip does not
support hardware RLE compression. It does
support hardware de-compression!
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| FDC37B72X_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 Pin Enhanced Super I/O Controller with ACPI Support |
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| FDC37B772QFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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