參數(shù)資料
型號(hào)： FDC37B72X
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 外設(shè)及接口
英文描述： 128 Pin Enhanced Super I/O Controller with ACPI Support
中文描述： MULTIFUNCTION PERIPHERAL, PQFP128
封裝： QFP-128
文件頁(yè)數(shù)： 143/244頁(yè)
文件大?。?/td> 1037K
代理商： FDC37B72X
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143
PME SUPPORT
The FDC37B72x offers support for PCI power
management events (PMEs). A power
management event is requested by a PCI
function via the assertion of the nPME signal.
The assertion and deassertion of nPME is
asynchronous to the PCI clock. In the
FDC37B72x, active transitions on the ring
indicator inputs nRI1 and nRI2 or the nRING
pin, active keyboard-data edges, active mouse-
data edges and GPIOs GP10-GP17 can directly
assert the nPME signal. In addition, if the
DEVINT_EN bit in the PME_EN 1 Register is
set, and if the EN_SMI_PME bit in the SMI_EN
2 register is set, then any of the SMI Events can
also generate a nPME. See the SCI/PME and
SMI/PME logic diagrams below.
nPME functionality is controlled by the runtime
registers
at
<PM1_BLK>+Ch
<PM1_BLK>+11h. The PME Enable bit,
PME_EN, globally controls PME Wake-up
events. When PME_EN is inactive, the nPME
signal can not be asserted. When PME_EN is
asserted, any wake source whose individual
PME Wake Enable register bit is asserted can
cause nPME to become asserted. The PME
Wake Status register indicates which wake
source has asserted the nPME signal. The PME
Status bit, PME_STS, is asserted by active
transitions of PME Wake sources. PME_STS
will become asserted independent of the state of
the global PME enable, PME_EN.
through
In the FDC37B72x the nPME pin is an open
drain, active low, driver. The FDC37B72x nPME
pin is fully isolated from other external devices
that might pull the PCI nPME signal low; i.e., the
PCI nPME signal is capable of being driven high
externally by another active device or pullup
even when the the FDC37B72x VDD is
grounded, providing VTR power is active. The
FDC37B72x nPME driver sinks 6mA at .55V
max (see section 4.2.1.1 DC Specifications,
page 122, in the PCI Local Bus Specification,
Revision 2.1).
ACPI, PME AND SMI REGISTERS
Logical Device A in the configuration section
contains the address pointer to the ACPI power
management register block, and PM1_BLK.
These are run-time registers; Included in the
PM1_BLK is an enable bit to allow the SCI
group interrupt to be routed to any interrupt or
onto the nPME/SCI pin. Note: See IRQ mux
control register for SCI/PME/SMI selection
function and pin configuration bits.
Register Description
The ACPI register model consists of a number
of fixed register blocks that perform designated
functions. A register block consists of a number
of registers that perform Status, Enable and
Control functions. The ACPI specification deals
with events (which have an associated interrupt
status and enable bits, and sometimes an
associated
control
function)
features. The status registers illustrate what
defined function is requesting ACPI interrupt
services (SCI). Any status bit in the ACPI
specification has the following attributes:
A.
Status bits are only set through some
defined “hardware event.”
B.
Unless otherwise noted, Status bits are
cleared by writing a “HIGH” to that bit
position, and upon VTR POR. Writing
a 0 has no effect.
C.
Status bits only generate interrupts
while their associated bit in the enable
register is set.
D.
Function bit positions in the status
register have the same bit position in
the
enable
exceptions to this rule, special status
bits have no enables).
and
control
register
(there
are
Note that this implies that if the respective
enable bit is reset and the hardware event
occurs, the respective status bit is set, however
no interrupt is generated until the enable bit is
set. This allows software to test the state of the
event (by examining the status bit) without
necessarily generating an interrupt. There are a
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