- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381841 > FDC37B72X (STANDARD MICROSYSTEMS CORP) 128 Pin Enhanced Super I/O Controller with ACPI Support PDF資料下載
參數(shù)資料
| 型號： | FDC37B72X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O Controller with ACPI Support |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 34/244頁 |
| 文件大?。?/td> | 1037K |
| 代理商： | FDC37B72X |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁第235頁第236頁第237頁第238頁第239頁第240頁第241頁第242頁第243頁第244頁
34
RESET
There are three sources of system reset on the
FDC: the RESET pin of the FDC, a reset
generated via a bit in the DOR, and a reset
generated via a bit in the DSR. At power on, a
Power On Reset initializes the FDC. All resets
take the FDC out of the power down state.
All operations are terminated upon a RESET,
and the FDC enters an idle state. A reset while
a disk write is in progress will corrupt the data
and CRC.
On exiting the reset state, various internal
registers are cleared, including the Configure
command information, and the FDC waits for a
new command. Drive polling will start unless
disabled by a new Configure command.
RESET Pin (Hardware Reset)
The RESET pin is a global reset and clears all
registers except those programmed by the
Specify command. The DOR reset bit is
enabled and must be cleared by the host to exit
the reset state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same.
Both will reset the FDC core, which affects drive
status information and the FIFO circuits. The
DSR reset clears itself automatically while the
DOR reset requires the host to manually clear it.
DOR reset has precedence over the DSR reset.
The DOR reset is set automatically upon a pin
reset. The user must manually clear this reset
bit in the DOR to exit the reset state.
MODES OF OPERATION
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of the IDENT and
MFM bits 3 and 2 respectively of LD8CRF0.
PC/AT mode
- (IDENT high, MFM a "don't
care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (FINTR
and DRQ can be hi Z), and TC and DENSEL
become active high signals.
PS/2 mode
- (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80
configuration and register set. The DMA bit of
the DOR becomes a "don't care", (FINTR and
DRQ are always valid), TC and DENSEL
become active low.
Model 30 mode
- (IDENT low, MFM low)
This
mode
supports
configuration and register set. The DMA enable
bit of the DOR becomes valid (FINTR and DRQ
can be hi Z), TC is active high and DENSEL is
active low.
PS/2
Model
30
DMA TRANSFERS
DMA transfers are enabled with the Specify
command and are initiated by the FDC by
activating the FDRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.
Note that if the DMA controller (i.e. 8237A) is
programmed to function in verify mode, a
pseudo read is performed by the FDC based
only on nDACK. This mode is only available
when the FDC has been configured into byte
mode (FIFO disabled) and is programmed to do
a read. With the FIFO enabled, the FDC can
perform the above operation by using the new
Verify command; no DMA operation is needed.
Two DMA transfer modes are supported for the
FDC: Single Transfer and Burst Transfer. In the
case of the single transfer, the DMA Req goes
active at the start of the DMA cycle, and the
DMA Req is deasserted after the nDACK. In the
case of the burst transfer, the Req
is held active
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FDC37B77X | 30 AMP MINIATURE POWER RELAY |
| FDC37B787-NS | Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR |
| FDC37B787QF | Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR |
| FDC37B78X | Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR |
| FDC37B80X | PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| FDC37B72X_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:128 Pin Enhanced Super I/O Controller with ACPI Support |
| FDC37B770 | 制造商:SMSC 制造商全稱:SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES |
| FDC37B771 | 制造商:SMSC 制造商全稱:SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES |
| FDC37B772 | 制造商:SMSC 制造商全稱:SMSC 功能描述:ENHANCED SUPER I/O CONTROLLER WITH WAKE UP FEATURES |
| FDC37B772QFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。