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參數(shù)資料
| 型號： | FDC37B72X |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | 128 Pin Enhanced Super I/O Controller with ACPI Support |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PQFP128 |
| 封裝： | QFP-128 |
| 文件頁數(shù)： | 126/244頁 |
| 文件大小： | 1037K |
| 代理商： | FDC37B72X |
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126
WATCH DOG TIMER
The FDC37B72x contains a Watch Dog Timer
(WDT). The Watch Dog Time-out status bit may
be mapped to an interrupt through the
WDT_CFG Configuration Register. It can also
be brought out on the GP12 or GP63 pins by
programming
the
configuration register.
corresponding
GPIO
The FDC37B72x's WDT has a programmable
time-out ranging from 1 to 255 minutes with one
minute resolution, or 1 to 255 seconds with 1
second resolution. The units of the WDT
timeout value are selected via bit[7] of the
WDT_TIMEOUT register (LD8:CRF1.7). The
WDT time-out value is set through the
WDT_VAL Configuration register. Setting the
WDT_VAL register to 0x00 disables the WDT
function (this is its power on default). Setting
the WDT_VAL to any other non-zero value will
cause the WDT to reload and begin counting
down from the value loaded. When the WDT
count value reaches zero the counter stops and
sets the Watchdog time-out status bit in the
WDT_CTRL Configuration Register. Note:
Regardless of the current state of the WDT, the
WDT time-out status bit can be directly set or
cleared by the Host CPU.
There are three system events which can reset
the WDT. These are a Keyboard Interrupt, a
Mouse Interrupt, or I/O reads/writes to address
0x201 (the internal or an external Joystick Port).
The effect on the WDT for each of these system
events may be individually enabled or disabled
through bits in the WDT_CFG configuration
register. When a system event is enabled
through the WDT_CFG register, the occurrence
of that event will cause the WDT to reload the
value stored in WDT_VAL and reset the WDT
time-out status bit if set. If all three system
events are disabled the WDT will inevitably time
out.
The Watch Dog Timer may be configured to
generate an interrupt on the rising edge of the
Time-out status bit. The WDT interrupt is
mapped to an interrupt channel through the
WDT_CFG Configuration Register. When
mapped to an interrupt the interrupt request pin
reflects the value of the WDT time-out status bit.
The host may force a Watch Dog time-out to
occur by writing a "1" to bit 2 of the WDT_CTRL
(Force WD Time-out) Configuration Register.
Writing a "1" to this bit forces the WDT count
value to zero and sets bit 0 of the WDT_CTRL
(Watch Dog Status). Bit 2 of the WDT_CTRL is
self-clearing.
LED
The FDC37B72x can directly drive an LED using
the alternate function of GP13 or GP61 (only
one may be used at at time). These pins are
active under VTR power so the LED may be
used in any system power state. The GPIO
used for the LED will initially default to an input;
the corresponding GPIO configuration register
must be programmed to configure the pin for the
LED function and as a push pull or an open
drain output. However, under VTR power the
LED must be configured as open drain, since
the pin cannot drive current under VTR power.
The polarity bit may be chosen as either non-
inverted or inverted (active high or active low).
The LED can be turned on and off or toggled at
a 1 Hertz rate with a 50 percent duty cycle.
When the GP13 or GP61 pin is configured as a
non-inverted, open drain output and the LED
function is chosen, the LED may be turned on
by writing ‘1’ the GP1 register bit 3 or the GP6
register bit 1. Clearing these bits will then turn
the LED off. The LED may be toggled as
described below. Note that the GPIO can
control the LED in its default GPIO function, but
it may only toggle if the LED function is chosen.
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| FDC37B772QFP | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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