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參數(shù)資料
| 型號(hào)： | EM78568 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8-BIT MICRO-CONTROLLER for FRS |
| 中文描述： | 8位微控制器為FRS |
| 文件頁數(shù)： | 37/54頁 |
| 文件大小： | 494K |
| 代理商： | EM78568 |
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EM78568
8-bit Micro-controller for FRS
__________________________________________________________________________________________________________________________________________________________________
* This specification are subject to be changed without notice.
07/28/2004 V3.5
Operation registers :
Address
R register
PAGE0
00xxxxxx
xx0x0000
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
00011x00
xxxxxxxx
0xxxx000
xxxx0000
00000000
R register
PAGE1
xxxx0000
xxxxxxxx
xxxxxx00
00000000
xxxxxxxx
11111111
00000000
00000000
11111111
IOC register
PAGE0
111x0000
11111111
11111111
11111111
11111111
00000000
xxxxxxxx
00000000
xxxxx000
00000000
IOC register
PAGE1
00000000
000000xx
00000000
00000000
0000000x
00000xxx
xxxxx0xx
00000000
00000000
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
VII.6 Wake-up
The controller has two types of sleep mode for power saving :
(1) SLEEP mode, RA(7) = 0 + "SLEP" instruction
The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or
PLL control (which has enable register), user has to turn it off by software.
(2) IDLE mode, RA(7) = 1 + "SLEP" instruction.
The controller will turn CPU off, but the crystal.
Wake-up from SLEEP mode
(1) WDT time out
(2) External interrupt
(3) /RESET pull low
All these cases will reset controller , and run the program at address zero. The status just like the power on reset.
Be sure to enable circuit at case (1) or (2).
Wake-up from IDLE mode
(1)WDT time out
(2) external interrupt
(3) internal interrupt like counters
All these cases, user has to enable circuit before entering IDLE mode. After wake-up, all the register will keep
values just like into "SLEP" instruction before.
At case (2) or (3), controller will wake up and jump to address 0x08 for interruption sub-routine. After finishing
sub-routine ("RETI" instruction), program will jump to the next instruction from "SLEP" instruction.
VII.7 Interrupt
RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask
register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the
interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the
interrupt service routine, the source of the interrupt can be determined by polling the flag bits in the RF register.
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