
EM78568
8-bit Micro-controller for FRS
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* This specification are subject to be changed without notice.
07/28/2004 V3.5
R1 (TCC)
TCC data buffer. Increased by 16.384KHz or by the instruction cycle clock (controlled by CONT register).
Written and read by the program as any other register.
R2 (Program Counter)
The structure is depicted in Fig. 5.
Generates 16k
×
13 on-chip PROGRAM ROM addresses to the relative programming instruction codes.
"JMP" instruction allows the direct loading of the low 10 program counter bits.
"CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.
"RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack.
"MOV R2, A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are
cleared to "0''.
"ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are
cleared to "0''.
"TBL" allows a relative address added to the current PC, and contents of the ninth and tenth bits don't change.
The most significant bit (A10~A13) will be loaded with the contents of bit PS0~PS3 in the status register (R5
PAGE0) upon the execution of a "JMP'', "CALL'', "ADD R2, A'', or "MOV R2, A'' instruction.
If an interrupt is triggered, PROGRAM ROM will jump to address 0x08 at page0. The CPU will store ACC,
R3 status and R5 PAGE automatically, and they will be restored after instruction RETI.
Fig.3 Program counter organization
R3 (Status, Page selection)
PAGE0 (Status flag, Page selection bits)
7
6
RPAGE2 RPAGE IOCPAGE
R/W-0
R/W-0
Bit 0(C) : Carry flag
Bit 1(DC) : Auxiliary carry flag
5
4
T
R
3
P
R
2
Z
1
0
C
DC
R/W
R/W-0
R/W
R/W
PC
A13 A12 A11 A10 A9 A8 A7~A0
0000
PAGE0 0000~03FF
0001
PAGE1 0400~07FF
1110
PAGE14 3800~3BFF
1111
PAGE15 3C00~3FFF
0010
PAGE2 0800~0BFF
STACK1
STACK2
STACK3
STACK4
STACK5
STACK6
STACK7
STACK8
STACK9
STACK10
STACK11
STACK12
STACK13
STACK14
STACK15
STACK16
CALL and
INTERRUPT
RET
RETL
RETI
ACC,R3,R5(PAGE)
R5(PAGE)
store
restore