
EM78568
8-bit Micro-controller for FRS
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* This specification are subject to be changed without notice.
07/28/2004 V3.5
VII. Functional Descriptions
VII.1 Operational Registers
Register configuration
Addr R PAGE0
00
Indirect addressing
01
TCC
02
PC
03
Page, Status
04
RAM bank, RSR
05
Port5 I/O data,
R PAGE registers
R PAGE1
IOC PAGE registers
IOC PAGE0
IOC PAGE1
Program ROM page
06
Port6 I/O data
07
Port7 I/O data
LCD RAM address
Port5 I/O control,
LCD bias control
Comparator control
LCD RAM data buffer
Port6 I/O control
Port6 switches
CTCSS detection output,
Data RAM bank
Port7 I/O control
Port7 pull high
08
Port8 I/O data
09
Port9 I/O data
0A
PLL, Main clock,
Data RAM address
Port8 I/O control
Port8 pull high
Data RAM data buffer
Port9 I/O control
Port9 switches
Comparator flag,
WDTE
DAC input data buffer
TONE2 control
DAC control,
2.5V ref control
0B
0C
PortC I/O data
0D
LCD control
Counter1 data
PortC I/O control
Port5 switch
Counter2 data
TONE1 control
Clock source(CN1,CN2)
Prescaler(CN1,CN2)
0E
Wake-up control,
0F
Interrupt flag
10
16 bytes
:
Common registers
1F
20
Bank0~Bank3
:
Common registers
3F
(32x8 for each bank)
DAC tone selection
TONE1 extra control,
CTCSS control switches
Interrupt mask
VII.2 Operational Register Detail Description
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction using R0
as register actually accesses data pointed by the RAM Select Register (R4).
Example:
Mov
A, @0x20
;store a address at R4 for indirect addressing
Mov
0x04, A
Mov
A, @0xAA
;write data 0xAA to R20 at bank0 through R0
Mov
0x00, A