
EM78568
8-bit Micro-controller for FRS
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* This specification are subject to be changed without notice.
07/28/2004 V3.5
RF (Interrupt status)
(Interrupt status register)
7
INT3
R/W-0
"1" means interrupt request, "0" means non-interrupt
Bit 0(TCIF) : TCC timer overflow interrupt flag
Set when TCC timer overflows.
Bit 1(CNT1) : counter1 timer overflow interrupt flag
Set when counter1 timer overflows.
Bit 2(CNT2) : counter2 timer overflow interrupt flag
Set when counter2 timer overflows.
Bit 3(INT0) : external INT0 pin interrupt flag
If PORT70 has a falling edge/rising edge (controlled by CONT register) trigger signal, CPU will set this bit.
Bit 4(INT1) : external INT1 pin interrupt flag
If PORT71 has a falling edge trigger signal, CPU will set this bit.
Bit 5(INT2) : external INT2 pin interrupt flag
If PORT72 has a falling edge trigger signal, CPU will set this bit.
Bit 6(DETO) : CTCSS tone detection interrupt flag
If CTCSS detection output signal(R7 PAGE1 bit 6) has an edge signal (falling edge, falling and rising
edge), CPU will set this bit.
Bit 7(INT3) : external INT3 pin interrupt flag
If PORT73 has a falling edge trigger signal, CPU will set this bit.
<Note> IOCF is the interrupt mask register. User can read and clear.
Trigger edge as the table
Signal
Trigger
TCC
Time out
COUNTER1
Time out
COUNTER2
Time out
INT0
Falling
Rising edge
INT1
Falling edge
INT2
Falling edge
DETO
Falling edge
Falling and rising edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : all are general purpose registers.
6
5
4
3
2
1
0
DETO
R/W-0
INT2
R/W-0
INT1
R/W-0
INT0
R/W-0
CNT2
R/W-0
CNT1
R/W-0
TCIF
R/W-0