
EM78568
8-bit Micro-controller for FRS
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* This specification are subject to be changed without notice.
07/28/2004 V3.5
Bit 6(PLLEN) : PLL's power control bit which is CPU mode control register
0/1
disable PLL/enable PLL
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
447.8293kHz ~17.9132MHz
Sub-clock
32.768kHz
switch
0
1
System clock
PLL circuit
ENPLL
CLK2 ~ CLK0
Fig.4 The relation between 32.768kHz and PLL
Bit 7(IDLE) : Sleep mode or IDLE mode control after using "SLEP" instruction.
0/1
SLEEP mode/IDLE mode.
This bit will decide SLEP instruction which mode to go.
The status after wake-up and the wake-up sources list as the table below.
Wakeup signal
SLEEP mode
RA(7,6)=(0,0)
+ SLEP
TCC time out
IOCF bit0=1
COUNTER1 time out
IOCF bit1=1
COUNTER2 time out
IOCF bit2=2
WDT time out
Reset and jump to
address 0
PORT8(0~3)
RE PAGE0 bit3 or
bit4 or bit5 or bit6 = 1
PORT7(0~3)
IOCF bit3 or bit4 or
bit5 or bit7=1
<Note> PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger
(controlled by CONT register bit7).
PORT7(1~3) 's wakeup functions are controlled by IOCF bit (4,5,7). They are falling edge trigger.
PORT80~PORT83’s wakeup function are controlled by RE PAGE0 bit 0 ~ bit 3. They are falling
edge trigger.
IDLE mode
RA(7,6)=(1,0)
+ SLEP
(1) Wake-up
(2) Jump to SLEP next instruction
No function
No function
(1) Wake-up
(2) Jump to SLEP next instruction
(1) Wake-up
(2) Jump to SLEP next instruction
(1) Wake-up
(2) Next instruction
(1) Wake-up
(2) Jump to SLEP next instruction
No function
Reset and Jump to
address 0
Reset and Jump to
address 0
(1) Wake-up
(2) Jump to SLEP next instruction