
EM78568
8-bit Micro-controller for FRS
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* This specification are subject to be changed without notice.
07/28/2004 V3.5
PAGE1 (DAC input data register)
7
6
DA7
DA6
R/W-1
R/W-1
Bit 0 ~ Bit 7 (DA0 to DA7) : DA converter data buffer
RC (PORTC0 I/O data, Counter1 data)
PAGE0 (PORT9 I/O data register)
7
6
5
-
-
-
Bit 0 (PC0) : PORTC0 I/O data register
User can use IOC register to define input or output this bit.
Bit 1 ~ Bit 7 :
(undefined) not allowed to use
PAGE1 (Counter1 data register)
Bit7
Bit6
Bit5
CN17
CN16
CN15
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 7 (CN10 ~ CN17) : Counter1's buffer that user can read and write.
Counter1 is a 8-bit up-counter with 8-bit prescaler that user can use RC PAGE1 to preset and read the
counter.(write
preset) After a interruption , it will reload the preset value.
Example for writing :
MOV 0x0C, A ; write the data at accumulator to counter1 (preset)
Example for reading :
MOV A, 0x0C ; read the data at counter1 to accumulator
RD (LCD control, Counter2 data)
PAGE0 (LCD driver control bits)
7
6
5
4
3
DETOED
-
-
-
-
R/W-0
Bit 0 (LCD_M) : LCD operation method including duty and frame frequency
Bit 1 ~ Bit 2 (LCD_C0 ~ LCD_C1) : LCD display control
LCD_C1 LCD_C0 LCD_M LCD Display Control
0
0
0
change duty
1
Disable(turn off LCD)
0
1
:
Blanking
1
1
:
LCD display enable
Ps. To change the display duty must set the "LCD_C1 ,LCD_C0" to "00".
The controller can drive LCD directly. The LCD block is made up of common driver, segment driver,
display LCD RAM, common output pins, segment output pins and LCD operating power supply. The basic
structure contains a timing control. This timing control uses the basic frequency 32.768KHz to generate the
proper timing for different duty and display access.
RD PAGE0 Bit 0 ~ Bit 2 are LCD control bits for LCD driver. These LCD control bits determine the duty,
the number of common and the frame frequency. The LCD display (disable, enable, blanking) is controlled
by Bit 1 and Bit 2. The driving duty is decided by Bit 0. The display data is stored in LCD RAM which
address and data access controlled by registers R5 PAGE1 and R6 PAGE1.
5
4
3
2
1
0
DA5
R/W-1
DA4
R/W-1
DA3
R/W-1
DA2
R/W-1
DA1
R/W-1
DA0
R/W-1
4
-
3
-
2
-
1
-
0
PC0
R/W
Bit4
CN14
R/W-0
Bit3
CN13
R/W-0
Bit2
CN12
R/W-0
Bit1
CN11
R/W-0
Bit0
CN10
R/W-0
2
1
0
LCD_C1 LCD_C0
R/W-0
LCD_M
R/W-0
R/W-0
Duty
1/4
1/2
:
:
Bias
1/3
1/3
:
: