
EM78568
8-bit Micro-controller for FRS
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* This specification are subject to be changed without notice.
07/28/2004 V3.5
Bit 2(Z) : Zero flag
Bit 3(P) : Power down bit
Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.
Bit 4(T) : Time-out bit
Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
EVENT
T
P
REMARK
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
Low pulse on /RESET
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page
Please refer to Fig.4 control register configuration for details.
0/1
page0 / page1
Bit 6(RPAGE) : change R5 ~ RE to another page
Please refer to Fig.4 control register configuration for details.
0/1
page0 / page1
Bit 7(RPAGE2) : change R5 ~ RE to R page2
(remain this bit to “0” unchanged)
0
The page for R5 ~ RE depends on Bit 6(RPAGE)
1
change R5 ~ RE to page2
R4 (RAM selection for common registers R20 ~ R3F))
(RAM selection register)
7
6
5
4
RB1
RB0
RSR5
RSR4
R/W-0
R/W-0
R/W
R/W
Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F
RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode.
Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F
These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to
R3F)..
Please refer to VII.1 Operational Registers for details.
0
0
1
1
x
0
1
0
1
x
x : don't care
3
2
1
0
RSR3
R/W
RSR2
R/W
RSR1
R/W
RSR0
R/W
R5 (PORT5 I/O data, Program page selection, LCD address)
PAGE0 (PORT5 I/O data register, Program page register)
7
6
5
4
P57
P56
P55
-
R/W
R/W
R/W
Bit 0 ~ Bit 3 (PS0 ~ PS3) : Program page selection bits
PS3
PS2
PS1
PS0
Program memory page (Address)
0
0
0
0
Page 0
0
0
0
1
Page 1
0
0
1
0
Page 2
0
0
1
1
Page 3
:
:
:
:
:
1
1
1
0
Page 14
1
1
1
1
Page 15
3
2
1
0
PS3
R/W-0
PS2
R/W-0
PS1
R/W-0
PS0
R/W-0