參數(shù)資料
型號(hào)： EDX5116ADSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁(yè)數(shù)： 71/78頁(yè)
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3C-E
Data Sheet E1033E30 (Ver. 3.0)
71
EDX5116ADSE
Serial Interface Transmit Timing
Figure 53 shows a timing diagram for the serial interface pins
of the memory component. This diagram represents a magni-
fied view of the pins and only a few clock cycles are shown.
The serial interface pins carry low-true signals: a high voltage
represents a logical zero and a low voltage represents a logical
one. Timing events are measured to and from the V
REF,RSL
level. Because timing intervals are measured in this fashion, it is
necessary to constrain the slew rate of the signals. The rise time
(t
OR,SI
) and fall time (t
OF,SI
) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = V
OL,SI
+ 0.2*(V
OH,SI
-V
OL,SI
)
50% = V
OL,SI
+ 0.5*(V
OH,SI
-V
OL,SI
)
80% = V
OL,SI
+ 0.8*(V
OH,SI
-V
OL,SI
)
There is one transmit window defined for the serial interface
data signal (SDO pins). This window has a maximum delay
time (t
Q,SI,MAX
) from the falling edge of the SCK clock signal
and a minimum delay time (t
Q,SI,MIN
) from the next falling
edge of the SCK clock signal.
When the memory component is not selected during a serial
device read transaction, it will simply pass the information on
the SDI input to the SDO output. This combinational propa-
gation delay parameter is t
P,SI
. The t
CYC,SCK
will need to be
increased during a serial read transaction (relative to the
t
CYC,SCK
value for a serial write transaction) because of the
accumulated propagation delay through all of the XDR DRAM
devices on the serial interface.
During Initialization, when the serial identification is deter-
mined, the SDI-to-SDO path is registered, so the t
CYC,SCK
value can be set to the same value as for serial write transac-
tions. See “Initialization” on page 46.
Figure 53
S erial Interfac e Transmit Waveforms
SCK
t
CYC,SCK
80%
20%
V
IL,SI
logic 1
V
IH,SI
logic 0
V
REF,RSL
t
L,SCK
t
H,SCK
t
F,SCK
t
R,SCK
80%
20%
V
OL,SI
logic 1
t
OR,SI
V
OH,SI
logic 0
V
REF,RSL
t
Q,SI,MAX
t
Q,SI,MIN
t
OF,SI
80%
20%
V
IL,SI
logic 1
V
IH,SI
logic 0
V
REF,RSL
SDI
t
P,SI
SDO
Combinational propagation from SDI to
SDO when the device is not selected
during a serial device read transaction.
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