參數(shù)資料
型號： EDX5116ADSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁數(shù)： 48/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3C-E
Data Sheet E1033E30 (Ver. 3.0)
48
EDX5116ADSE
XDR DRAM Pattern Load with WDSL Reg
The XDR memory system requires a method of deterministi-
cally loading pattern data to XDR DRAMs before beginning
Receive Timing Calibration (RX TCAL). The method
employed by the XDR DRAMs to achieve this is called Write
Data Serial Load (WDSL). A WDSL packet sends one-byte of
serial data which is serially shifted into a holding register within
the XDR DRAM. Initialization software sends a sequence of
WDSL packets, each of which shifts the new byte in and
advances the shifter by 8 positions. In this way, XDR DRAMs
of varying widths can be loaded with a single command type.
Each sequence of WDSL packets will load one full column of
data to the internal holding register of the target XDR DRAM.
Depending upon the ratio of native device width to pro-
grammed width, there may be more than one sub-column per
column. After loading a full column, a series of WR com-
mands will be issued to sequentially transfer each sub-column
of the column to the XDR DRAM core(s), based upon the
SC[3:0] bits.
.
Table 10
XDR DRAM WDSL-to-Core/DQ/SC Map (First Generation x16/x8/x4 XDR DRAM , BL=16)
DQ Pins Used
Core Word
WDSL Core Word
Load Order
x16
x8
x4
x4
x8
x16
WD[n][15:0]
SC[3:2]
=xx
SC[3:2]
= 0x
SC[3:2]
= 1x
SC[3:2]
= 00
SC[3:2]
= 01
SC[3:2]
= 10
SC[3:2]
= 11
LOGICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
DQ0
DQ0
DQ0
WD[0][15:0]
WDSL Word 8
1
1
0
1
0
0
0
DQ1
DQ1
DQ1
WD[1][15:0]
WDSL Word 7
1
1
0
1
0
0
0
DQ2
DQ2
DQ2
WD[2][15:0]
WDSL Word 12
1
1
0
1
0
0
0
DQ3
DQ3
DQ3
WD[3][15:0]
WDSL Word 3
1
1
0
1
0
0
0
DQ0
DQ4
DQ4
WD[4][15:0]
WDSL Word 10
1
1
0
0
1
0
0
DQ1
DQ5
DQ5
WD[5][15:0]
WDSL Word 5
1
1
0
0
1
0
0
DQ2
DQ6
DQ6
WD[6][15:0]
WDSL Word 14
1
1
0
0
1
0
0
DQ3
DQ7
DQ7
WD[7][15:0]
WDSL Word 1
1
1
0
0
1
0
0
DQ0
DQ0
DQ8
WD[8][15:0]
WDSL Word 9
1
0
1
0
0
1
0
DQ1
DQ1
DQ9
WD[9][15:0]
WDSL Word 6
1
0
1
0
0
1
0
DQ2
DQ2
DQ10
WD[10][15:0]
WDSL Word 13
1
0
1
0
0
1
0
DQ3
DQ3
DQ11
WD[11][15:0]
WDSL Word 2
1
0
1
0
0
1
0
DQ0
DQ4
DQ12
WD[12][15:0]
WDSL Word 11
1
0
1
0
0
0
1
DQ1
DQ5
DQ13
WD[13][15:0]
WDSL Word 4
1
0
1
0
0
0
1
DQ2
DQ6
DQ14
WD[14][15:0]
WDSL Word 15
1
0
1
0
0
0
1
DQ3
DQ7
DQ15
WD[15][15:0]
WDSL Word 0
1
0
1
0
0
0
1
PHYSICAL VIEW OF XDR DRAM
Word Written (1 = Written, 0 = Not Written)
DQ2
DQ6
DQ14
WD[14][15:0]
WDSL Word 15
1
0
1
0
0
0
1
DQ6
WD[6][15:0]
WDSL Word 14
1
1
0
0
1
0
0
DQ2
DQ10
WD[10][15:0]
WDSL Word 13
1
0
1
0
0
1
0
DQ2
WD[2][15:0]
WDSL Word 12
1
1
0
1
0
0
0
DQ0
DQ4
DQ12
WD[12][15:0]
WDSL Word 11
1
0
1
0
0
0
1
DQ4
WD[4][15:0]
WDSL Word 10
1
1
0
0
1
0
0
DQ0
DQ8
WD[8][15:0]
WDSL Word 9
1
0
1
0
0
1
0
DQ0
WD[0][15:0]
WDSL Word 8
1
1
0
1
0
0
0
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