- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384283 > EDX5116ADSE-3C-E (ELPIDA MEMORY INC) 512M bits XDR⑩ DRAM PDF資料下載
參數(shù)資料
| 型號： | EDX5116ADSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | ROHS COMPLIANT, FBGA-104 |
| 文件頁數(shù)： | 6/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE-3C-E |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Data Sheet E1033E30 (Ver. 3.0)
6
EDX5116ADSE
List of Figures
XDR DRAM Device Write and Read Transactions .....3
512Mb (8x4Mx16) XDR DRAM Block Diagram ..........9
Request Packet Formats ..............................................11
ACT-, RD-, WR-, PRE-to-ACT Packet Interactions . 16
ACT-, RD-, WR-, PRE-to-RD Packet Interactions ... 17
ACT-, RD-, WR-, PRE-to-WR Packet Interactions ... 18
ACT-, RD, WR-, PRE-to-PRE Packet Interactions .. 19
Request Scheduling Examples ................................... 21
Write Transactions .....................................................23
Read Transactions ......................................................25
Interleaved Transactions ............................................27
Write/Read Interaction ..............................................29
Propagation Delay ...................................................... 31
Serial Write Transaction .............................................33
Serial Read Transaction — Selected DRAM ..............33
Serial Read Transaction — Non-selected DRAM .....33
Serial Identification (SID) Register ............................34
Configuration (CFG) Register ....................................35
Power Management (PM) Register ............................35
Write Data Serial Load (WDSL) Control Register .....35
RQ Scan High (RQH) Register .................................36
RQ Scan Low (RQL) Register ....................................36
Refresh Bank (REFB) Control Register .....................36
Refresh High (REFH) Row Register .........................37
Refresh Middle (REFM) Row Register .....................37
Refresh Low (REFL) Row Register ...........................37
IO Configuration (IOCFG) Register ..........................37
Current Calibration 0 (CC0) Register ........................ 38
Current Calibration 1 (CC1) Register ......................... 38
Read Only Memory 0 (ROM0) Register .................... 38
Read Only Memory 1 (ROM1) Register .................... 38
TEST Register ............................................................ 39
Delay (DLY) Control Register ................................... 39
Refresh Transactions ..................................................41
Calibration Transactions ............................................ 43
Power State Management .......................................... 45
Serial Interface System Topology .............................. 46
Initialization Timing for XDR DRAM[k] Device .... 46
Multiplexers for Dynamic Width Control .................. 50
D-to-S and S-to-Q Mapping for Dynamic Width Control
51
Byte Mask Logic ........................................................ 52
Write-Masked (WRM) Transaction Example ........... 53
Write/Read Interaction — No ERAW Feature ......... 54
Write/Read Interaction — ERAW Feature ............... 54
XDR DRAM Block Diagram with Bank Sets .......... 55
Simultaneous Activation — tRR-D Cases ................. 56
Simultaneous Precharge — tPP-D Cases .................. 57
Clocking Waveforms .................................................. 64
RSL RQ Receive Waveforms ..................................... 65
DRSL DQ Receive Waveforms .................................. 67
DRSL DQ Transmit Waveforms ................................ 69
Serial Interface Receive Waveforms ........................... 70
Serial Interface Transmit Waveforms .........................71
Equivalent Circuits for Package Parasitic ................. 73
CSP x16 Package - Pin Numbering (top view) .......... 75
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| EDZ22B | LED 5MM 563NM HI GRN WATER CLEAR |
| EDZ24B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
| EDXSPECTRUMDATA/F8853801VGA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R8512701VZA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R9468002VHA | 制造商:Analog Devices 功能描述:DATA - Literature |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。