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參數(shù)資料
| 型號： | EDX5116ADSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | ROHS COMPLIANT, FBGA-104 |
| 文件頁數(shù)： | 42/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE-3C-E |
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Data Sheet E1033E30 (Ver. 3.0)
42
EDX5116ADSE
Calibration Transactions
Figure 35 shows the calibration transaction diagrams for the
XDR DRAM device. There is one calibration operation sup-
ported: calibration of the output current level I
OL
for each
DQi and DQNi pin.
The output current calibration sequence is shown in the upper
diagram. It begins when a period of t
CMD-CALC
is observed
after the last RQ packet (with command “CMD a” in this
example). No request packets should be issued in this period.
A COLX packet with a”CALC b” command is then issued to
start the current calibration sequence. A period of t
CALCE
is
observed after this packet. No request packets should be issued
during this period.
A COLX packet with a “CALE c” command is then issued to
end the current calibration sequence. A period of t
CALE-CMD
is
observed after this packet. No request packets should be issued
during this period. The first request packet may then be issued
(with command “CMD d” in this example).
A second current calibration sequence must be started within
an interval of t
CALC
. In this example, the next COLX packet
with a “CALC e” command starts a subsequent sequence.
The dynamic termination calibration sequence is shown in the
lower diagram. Note that this memory component does not
use this sequence; termination calibration is performed during
the manufacturing process. However, the termination sequence
shown will be issued by the controller for those memory com-
ponents which do use a periodic calibration mechanism.
It begins when a period of t
CMD-CALZ
is observed after the
packet at edge T
0
(with command CMDa in this example). No
request packets should be issued in this period.
A COLX packet with a CALZ command is then issued at edge
T
3
to start the termination calibration sequence. A second
period of t
CALZE
is observed after this packet. No request
packets should be issued during this period.
A COLX packet with a CALE command is then issued at edge
T
6
to end the termination calibration sequence. A third period
of t
CALE-CMD
is observed after this packet. No request packets
should be issued during this period. The first request packet
may be issued at edge T
12
(with command CMDd in this exam-
ple).
A second termination calibration sequence must be started
within an interval of t
CALZ
. In this example, the next COLX
packet with a CALZ command occurs at edge T
20
.
Note that the labels for the CFM clock edges (of the form T
i
)
are not to scale, and are used to identify events in the diagrams.
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| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| EDZ22B | LED 5MM 563NM HI GRN WATER CLEAR |
| EDZ24B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
| EDXSPECTRUMDATA/F8853801VGA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R8512701VZA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R9468002VHA | 制造商:Analog Devices 功能描述:DATA - Literature |
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