- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384283 > EDX5116ADSE-3C-E (ELPIDA MEMORY INC) 512M bits XDR⑩ DRAM PDF資料下載
參數(shù)資料
| 型號(hào)： | EDX5116ADSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR⑩ DRAM |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | ROHS COMPLIANT, FBGA-104 |
| 文件頁數(shù)： | 40/78頁 |
| 文件大?。?/td> | 3311K |
| 代理商： | EDX5116ADSE-3C-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當(dāng)前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Data Sheet E1033E30 (Ver. 3.0)
40
EDX5116ADSE
Maintenance Operations
Refresh Transactions
Figure 34 contains two timing diagrams showing examples of
refresh transactions. The top timing diagram shows a single
refresh operation. Bank Ba is assumed to be closed (in a pre-
charged state) when a REFA command is received in a ROWP
packet on clock edge T
0
. The REFA command causes the row
addressed by the REFr register (REFH/REFM/REFL) to be
opened (sensed) and placed in the sense amp array for the
bank.
Note that the REFA and REFI commands are similar to the
ACT command functionally; both specify a bank address and
delay value, and both cause the selected bank to open (to
become sensed.) The difference is that the ACT command is
accompanied by a row address in the ROWA packet, while the
REFA and REFI commands use a row address in the REFr
register (REFH/REFM/REFL).
After a time t
RAS
, a ROWP packet with REFP command to
bank Ba is presented. This causes the bank to be closed (pre-
charged), leaving the bank in the same state as when the refresh
transaction began.
Note that the REFP command is equivalent to the PRE com-
mand functionally; both specify a bank address and delay value,
and both cause the selected bank to close (to become pre-
charged).
After a time t
RP
, another ROWP packet with REFA command
to bank Bb is presented (banks Ba and Bb are the same in this
example). This starts a second refresh cycle. Each refresh
transaction requires a total time t
RC
= t
RAS
+ t
RP
, but refresh
transactions to different banks may be interleaved like normal
read and write transactions.
Each row of each bank must be refreshed once in every t
REF
interval. This is shown with the fourth ROWP packet with a
REFA command in the top timing diagram.
Interleaved Refresh Transactions
The lower timing diagram in Figure 34 represents one way a
memory controller might handle refresh maintenance in a real
system.
A series of eight ROWP packets with REFA commands
(except for the last which is a REFI command) are presented
starting at edge T
0
. The packets are spaced with intervals of
t
RR
. Each REFA or REFI command is addressed to a different
bank (Ba through Bh) but uses the same row address from the
REFr (REFH/REFM/REFL) register. The eighth REFI com-
mand uses this address and then increments it so the next set
of eight REFA/REFI commands will refresh the next set of
rows in each bank.
A series of eight ROWP packets with REFP commands are
presented effectively at edge T
10
(a time t
RAS
after the first
ROWP packet with a REFA command). The packets are
spaced with intervals of t
PP
. Like the REFA/REFI commands,
each REFP command is addressed to a different bank (Ba
through Bh).
This burst of eight refresh transactions fully utilizes the mem-
ory component. However, other read and write transactions
may be interleaved with the refresh transactions before and
after the burst to prevent any loss of bus efficiency. In other
words, a ROWA packet with ACT command for a read or write
could have been presented at edge T
-4
(a time t
RR
before the
first refresh transaction starts at edge T
0
). Also, a ROWA
packet with ACT command for a read or write could have been
presented at edge T
36
(a time t
RR
after the last refresh transac-
tion starts at edge T
32
). In both cases, the other request packets
for the interleaved read or write accesses (the precharge com-
mands and the read or write commands) could be slotted in
among the request packets for the refresh transactions.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3A-E | 512M bits XDR⑩ DRAM |
| EDZ20B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
| EDZ22B | LED 5MM 563NM HI GRN WATER CLEAR |
| EDZ24B | Low Current Operation at 250 ，Low Reverse Leakage,Low Noise Zener Diode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ADSE-4D-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR⑩ DRAM |
| EDXSPECTRUMDAT/5962R8773901VDA | 制造商:Analog Devices 功能描述:SPECTRUM ANALYSIS - Literature |
| EDXSPECTRUMDATA/F8853801VGA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R8512701VZA | 制造商:Analog Devices 功能描述:DATA - Literature |
| EDXSPECTRUMDATA/R9468002VHA | 制造商:Analog Devices 功能描述:DATA - Literature |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。