參數(shù)資料
型號： EDX5116ADSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁數(shù)： 51/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3C-E
Data Sheet E1033E30 (Ver. 3.0)
51
EDX5116ADSE
The block diagram in Figure 39 indicates that the Dynamic
Width logic is positioned after the serial-to-parallel conversion
(demux block) in the data receiver block and before the paral-
lel-to-serial conversion (mux block) in the data transmitter
block (see also the block diagram in Figure 2). The block dia-
gram is shown in this manner so the functionality of the logic
can be made as clear as possible. Some implementations may
place this logic in the data receiver and transmitter blocks, per-
forming the mapping in Figure 40 on the serial data rather than
the parallel data. However, this design choice will not affect the
functionality of the Dynamic Width logic; it is strictly an imple-
mentation decision.
Figure 40
D-to-S and S -to-Q Mapping for Dynamic Width Control
WIDTH[2:0]=000 (x1 device width)
000
S[0][15:0]
001
S[1][15:0]
010
S[2][15:0]
011
S[3][15:0]
100
S[4][15:0]
101
S[5][15:0]
110
S[6][15:0]
111
S[7][15:0]
S1000
S[8][15:0]
Q[0][15:0]
S[9][15:0]
WIDTH[2:0]=001 (x2 device width)
000x
S[4,0][15:0]
001x
S[5,1][15:0]
010x
S[6,2][15:0]
011x
S[7,3][15:0]
100x
Q[1:0][15:0]
S[11:10][15:0]
WIDTH[2:0]=010 (x4 device width)
0xx
1100
S[6,2,4,0][15:0]
S[12][15:0]
1xx
1101
S[7,3,5,1][15:0]
S[13][15:0]
S1110
WIDTH[2:0]=011 (x8 device width)
WIDTH[2:0]=010 (x4 device width)
xxx
00xx
S[7:0][15:0]
S[3:0][15:0]
SC01xx
D[7:0][15:0]
1001
1010
S[10][15:0]
1011
S[11][15:0]
Q[3:0][15:0]
1111
S[15][15:0]
SC[3:0]
D[0][15:0]
Q[0][15:0]
D[1:0][15:0]
101x
110x
S[13:12][15:0]
111x
S[15:14][15:0]
SC[3:0]
D[1:0][15:0]
Q[1:0][15:0]
Q[7:0][15:0]
10xx
S[11:8][15:0]
11xx
S[15:12][15:0]
SC[3:0]
D[3:0][15:0]
Q[3:0][15:0]
WIDTH[2:0]=011 (x8 device width)
0xxx
S[7:0][15:0]
1xxx
S[15:8][15:0]
SC[3:0]
D[7:0][15:0]
Q[7:0][15:0]
WIDTH[2:0]=100 (x16 device width)
xxxx
S[15:0][15:0]
SC[3:0]
D[15:0][15:0]
Q[15:0][15:0]
a
a
a) EDX5116ADSE does not support
×
1 and
×
2 device width.
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