參數(shù)資料
型號(hào)： EDX5116ADSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁數(shù)： 38/78頁
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3C-E
Data Sheet E1033E30 (Ver. 3.0)
38
EDX5116ADSE
Figure 28
Current Calibration 0 (CC0) Register
Figure 29
Current Calibration 1 (CC1) Register
Figure 30
Read Only Memory 0 (ROM0) Register
Figure 31
Read Only Memory 1 (ROM1) Register
7
6
5
4
3
2
1
0
Read/write register
CC0[7:0] resets to 00001111
2
CCVALUE0[5:0]
reserved
CCVALUE0[5:0] - Current calibration value field.
This field controls the amount of current drive for the even-num-
bered DQ and DQN pins.
Current Calibration 0 Register
SADR[7:0]: 00010000
2
7
6
5
4
3
2
1
0
Read/write register
CC1[7:0] resets to 00001111
2
CCVALUE1[5:0]
reserved
CCVALUE1[5:0] - Current calibration value field.
This field controls the amount of current drive for the odd-num-
bered DQ and DQN pins.
Current Calibration 1 Register
SADR[7:0]: 00010001
2
7
6
5
4
3
2
MASK[3:0]
1
0
Read-only register
ROM0[7:0] resets to 0010mmmm
MASK[3:0] - Version number of mask (0001
2
is first version).
VENDOR[3:0] - Vendor number for component:
0010 - Elpida
Read Only Memory 0 Register
SADR[7:0]: 00010110
2
Vreserved
7
6
5
4
3
2
1
0
Read-only register
ROM0[7:0] resets to bbrrrccc
CB[2:0] - Column address bits: #bits = 6 +CB[2:0]
RB[2:0] - Row address bits: #bits = 10 +RB[2:0]
BB[1:0] - Bank address bits: #bits = 2 +BB[1:0]
These three fields indicate how many column, row, and bank
address bits are present. An offset of {6,10,2} is added to the
field value to give the number of address bits.
Read Only Memory 1 Register
SADR[7:0]: 00010111
2
CB[2:0]
RB[2:0]
BB[1:0]
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