參數(shù)資料
型號(hào)： EDX5116ADSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR⑩ DRAM
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： ROHS COMPLIANT, FBGA-104
文件頁(yè)數(shù)： 52/78頁(yè)
文件大?。?/td> 3311K
代理商： EDX5116ADSE-3C-E
Data Sheet E1033E30 (Ver. 3.0)
52
EDX5116ADSE
Write Masking
Figure 41 shows the logic used by the XDR DRAM device
when a write-masked command (WRM) is specified in a
COLM packet. This masking logic permits individual bytes of a
write data packet to be written or not written according to the
value of an eight bit write mask M[7:0].
In Figure 41, there are 16 sets of 16 bit signals forming the
D1[15:0][15:0] input bus for the Byte Mask block. These are
treated as 2x16 8-bit bytes:
D1[15][15:8]
D1[15][7:0]
...
D1[1][15:8]
D1[1][7:0]
D1[0][15:8]
D1[0][7:0]
The eight bits of each byte is compared to the value in the byte
mask field (M[7:0]). If they are not equal (NE), then the corre-
sponding write enable signal (WE) is asserted and the byte is
written into the sense amplifier. If they are equal, then the cor-
responding write enable signal (WE) is deasserted and the byte
is not written into the sense amplifier.
In the example of Figure 41, a WRM command performs a
masked write of a 32-byte data packet to a single memory
device connected to the RQ bus (and receiving the command).
It is the job of the memory controller to search the 32 bytes to
find an eight bit data value that is not used and place it into the
M[7:0] field. This will always be possible because there are 256
possible 8-bit values and there are only 32 possible values used
in the bytes in the data packet.
Figure 41
Byte Mask Logic
Note that other systems might use a data transfer size that is
different than the 32 bytes per t
CC
interval per RQ bus that is
used in the example in Figure 41.
Figure 42 shows the timing of two successive WRM com-
mands in COLM packets. The timing is identical to that of two
successive WR commands in COL packets. The one difference
Byte Mask (WR)
S[0][7:0]
8
D1[0][7:0]
8
M[7:0]
Compare
8
NE
Dynamic Width Demux (WR)
16x16
16x16
Dynamic Width Mux (RD)
16x16
S[15:0][15:0]
16x16
D[15:0][15:0]
WIDTH[2:0]
SC[3:0]
WIDTH[2:0]
SC[3:0]
4+3
4+3
Q[15:0][15:0]
D1[15:0][15:0]
16x16
M[7:0]
8
1
8
D1[0][7:0]
8
S[0][15:8]
8
D1[0][15:8]
8
Compare
8
NE
1
8
D1[0][15:8]
8
8
8
Compare
8
NE
1
8
D1[15][7:0]
8
8
8
Compare
8
NE
1
8
D1[15][15:8]
8
S[15][15:8]
WE-MSB
[15]
S[15][7:0]
D1[15][15:8]
D1[15][7:0]
WE-LSB
[15]
WE-MSB
[0]
WE-LSB
[0]
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