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參數(shù)資料
| 型號： | EDX5116ABSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | LEAD FREE, FBGA-104 |
| 文件頁數(shù)： | 66/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE-3C-E |
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Preliminary Data Sheet E0643E30 (Ver. 3.0)
66
EDX5116ABSE
DRSL DQ Receive Timing
Figure 50 shows a timing diagram for receiving write data on
the DQ/DQN data pins of the memory component. This dia-
gram represents a magnified view of the pins and shows only a
few clock cycles are shown (CFM and CFMN are the clock sig-
nals). Timing events are measured to and from the primary
CFM/CFMN crossing point in which CFM makes its high-
voltage-to-low-voltage transition. The DQ15..0/DQN15..0
signals are high-true: a low voltage represents a logical zero and
a high voltage represents a logical one. They are also differen-
tial — timing events on the DQ15..0/DQN15..0 pins are mea-
sured to and from the point that each differential pair crosses.
Because timing intervals are measured in this fashion, it is nec-
essary to constrain the slew rate of the signals. The rise time
(t
IR,DQ
) and fall time (t
IF,DQ
) of the signals are measured from
the 20% and 80% points of the full-swing levels.
20% = V
IL,DQ
+ 0.2*(V
IH,DQ
-V
IL,DQ
)
80% = V
IL,DQ
+ 0.8*(V
IH,DQ
-V
IL,DQ
)
There are 16 data receiving windows defined for each
DQ15..0/DQN15..0 pin pair. The receiving windows for a
particular DQi/DQNi pin pair is referenced to an offset
parameter t
DOFF,DQi
(the index “i” may take on the values {0,
1, ..15} and refers to each of the DQ15..0/DQN15..0 pin
pairs).
The t
DOFF,DQi
parameter determines the time between the pri-
mary CFM/CFMN crossing point and the offset point for the
DQi/DQNi pin pair. The 16 receiving windows are placed at
times t
DOFF,DQi
+(j/8)*t
CYCLE
(the index “j” may take on the
values {0,1, 2, ..15} and refers to each of the receiving win-
dows for the DQi/DQNi pin pair).
The offset values t
DOFF,DQi
for each of the 16 DQi/DQNi pin
pairs can be different. However, each is constrained to lie
inside the range {t
DOFF,MIN ,
t
DOFF,MAX
}. Furthermore, each
offset value t
DOFF,DQi
is static and will not change during sys-
tem operation. Its value can be determined at initialization.
The 16 receiving windows (j=0..15) for the first pair DQ0/
DQN0 are labeled “0” through “15”. Each window has a set
time (t
S,RQ
) and a hold time (t
H,RQ
) measured around a point
t
DOFF,DQ0
+(j/8)*t
CYCLE
after the primary CFM/CFMN
crossing point.
The 16 receiving windows (j=0..15) for the each of the other
pairs DQi/DQNi are also labeled “0” through “15”. Each win-
dow has a set time (t
S,RQ
) and a hold time (t
H,RQ
) measured
around a point t
DOFF,DQi
+(j/8)*t
CYCLE
after the primary
CFM/CFMN crossing point.
相關PDF資料 |
PDF描述 |
|---|---|
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ADSE | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ACSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
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