- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384283 > EDX5116ABSE-3C-E (ELPIDA MEMORY INC) 512M bits XDR DRAM (32M words ?16 bits) PDF資料下載
參數(shù)資料
| 型號： | EDX5116ABSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | LEAD FREE, FBGA-104 |
| 文件頁數(shù)： | 47/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE-3C-E |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
Preliminary Data Sheet E0643E30 (Ver. 3.0)
47
EDX5116ABSE
previously been sampled one). This interval (measured in
t
CYC,SCK
units) will be equal to the index [k] of the XDR
DRAM device along the serial interface bus. In this example, k
is equal to 4.
This is because each XDR DRAM device will drive its SDO
output zero around the SCK edge a time t
SDI-SDO,00
after its
SDI input is sampled zero.
In other words, the XDR DRAM[0] device will see RST and
SDI both sampled zero on the same edge S
12
(t
RST-SDI,00
will
be 0*t
CYC,SCK
units), and will drive its SDO to zero around the
subsequent edge (S
13
).
The XDR DRAM[1] device will see SDI sampled zero on edge
S
13
(t
RST-SDI,00
will be 1*t
CYC,SCK
units), and will drive its
SDO to zero around the subsequent edge (S
14
).
The XDR DRAM[2] device will see SDI sampled zero on edge
S
14
(t
RST-SDI,00
will be 2*t
CYC,SCK
units), and will drive its
SDO to zero around the subsequent edge (S
15
).
This continues until the last XDR DRAM device drives the
SRD input of the controller. Each XDR DRAM device con-
tains a state machine which measures the interval t
RST-SDI,00
between the edges in which RST and SDI are both sampled
zero, and uses this value to set the SID[5:0] field of the SID
(Serial Identification) register. This value allows directed read
and write transactions to be made to the individual XDR
DRAM devices. Table 9 summarizes the range of the timing
parameters used for initialization by the serial interface bus.
XDR DRAM Initialization Overview
[1] Apply voltage toVDD, VTERM, and VREF pins. VTERM
and VREF voltages must be less or equal to VDD voltage at all
times. Wait a time interval t
COREINIT
.
[2] Assert RST, SCK, SDI, and CMD to logical zero. Then:
- Pulse SCK to logical one, then to logical zero four times.
- Assert RST to logical one. Reset circuit places XDR
DRAM into low-power state (identical to power-on reset).
- Perform remaining initialization sequence in Figure 38.
[3] XDR DRAM has valid Serial ID and all registers have
default values that are defined in Figure 17 through Figure 33.
[4] Perform broadcast or directed register writes to adjust regis-
ters which need a value different from their default value.
[5] Perform Powerdown Exit sequence shown in Figure 36.
This includes the activity from SCK cycle S
0
through the final
REFP command.
[6] Perform termination/current calibration. The CALZ/
CALE sequence shown in Figure 35 is issued 128 times, then
the CALC/CALE sequence is issued 128 times. After this, each
sequence is issued once every t
CALZ
or t
CALC
interval.
[7] Condition the XDR DRAM banks by performing a REFA/
REFI activate and REFP precharge operation to each bank
eight times. This can be interleaved to save time. The row
address for the activate operation will step through eight suc-
cessive values of the REFr registers. The sequence between
cycles T
0
and T
32
in the Interleaved Refresh Example in
Figure 34 could be performed eight times to satisfy this condi-
tioning requirement.
Table 9
Initialization Timing Parameters
Symbol
Parameter
Minimum
Maximum
Units
Figure(s)
t
RST,10
Number of cycles between RST being sampled one and RST being
sampled zero.
2
-
t
CYC,SCK
-
t
RST-SDO,11
Number of cycles between RST being sampled one and SDO being
driven to one.
1
1
t
CYC,SCK
-
t
RST-SDI,00
Number of cycles between RST being sampled zero (after being sam-
pled one for t
RST,10,MIN
or more cycles) and SDI being sampled zero.
This will be equal to the index [k] of the XDR DRAM device along
the serial interface bus.
0
63
t
CYC,SCK
-
t
SDI-SDO,00
Number of cycles between SDI being sampled one (after RST has
been sampled one for t
RST,10,MIN
or more cycles and is then sampled
zero) and SDO being driven to one.
1
1
t
CYC,SCK
-
t
RST-SCK
The number of SCK falling edges after the first SCK falling edge in
which RST is sampled one.
20
-
t
CYC,SCK
-
相關PDF資料 |
PDF描述 |
|---|---|
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ADSE | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ACSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。