參數(shù)資料
型號： EDX5116ABSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： LEAD FREE, FBGA-104
文件頁數(shù)： 44/78頁
文件大?。?/td> 3611K
代理商： EDX5116ABSE-3C-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
44
EDX5116ABSE
Power State Management
Figure 36 shows power state transition diagrams for the XDR
DRAM device. There are two power states in the XDR
DRAM: Powerdown and Active. Powerdown state is to be used
in applications in which it is necessary to shut down the CFM/
CFMN clock signals. In this state, the contents of the storage
cells of the XDR DRAM will be retained by an internal state
machine which performs periodic refresh operations using the
REFB and REFr control registers.
The upper diagram shows the sequence needed for Power-
down entry. Prior to starting the sequence, all banks of the
XDR DRAM must be precharged so they are left in a closed
state. Also, all 2
3
banks must be refreshed using the current
value of the REFr registers,
and the REFr registers must NOT be
incremented with the REFI command at the end of this special set of
refresh transactions
. This ensures that no matter what value has
been left in the REFB register, no row of any bank will be
skipped when automatic refresh is first started in Powerdown.
There may be some banks at the current row value in the REFr
registers that are refreshed twice during the Powerdown entry
process.
After the last request packet (with the command CMDa in the
upper diagram of the figure), an interval of t
CMD-PDN
is
observed. No request packets should be issued during this
period.
A COLX packet with the PDN command is issued after this
interval, causing the XDR DRAM to enter Powerdown state
after an interval of t
PDN-ENTRY
has elapsed (this is the parame-
ter that should be used for calculating the power dissipation of
the XDR DRAM). The CFM/CFMN clock signals may be
removed a time t
PDN-CFM
after the COLX packet with the
PDN command. Also, the termination voltage supply may be
removed (set to the ground reference) from the VTERM pins a
time t
PDN-CFM
after the COLX packet with the PDN com-
mand. The voltage on the DQ/DQN pins will follow the volt-
age on the VTERM pins during Powerdown entry.
When the XDR DRAM is in Powerdown, an internal fre-
quency source and state machine will automatically generate
internal refresh transactions. It will cycle through all 2
3
state
combinations of the REFB register. When the largest value is
reached and the REFB value wraps around, the REFr register
is incremented to the next value. The REFB and REFr values
select which bank and which row are refreshed during the next
automatic refresh transaction.
The lower diagram shows the sequence needed for Powerdown
exit. The sequence is started with a serial broadcast write (SBW
command) transaction using the serial bus of the XDR
DRAM. This transaction writes the value “00000001” to the
Power Management (PM) register (SADR=”00000011”) of all
XDR DRAMs connected to the serial bus. This sets the PX bit
of the PM register, causing the XDR DRAMs to return to
Active power state.
The CFM/CFMN clock signals must be stable a time t
CFM-
PDN
before the end of the SBW transaction. Also, the termina-
tion voltage supply must be restored to its normal operating
point (V
TERM,DRSL
) on the VTERM pins a time t
CFM-PDN
before the end of the SBW transaction. The voltage on the
DQ/DQN pins will follow the voltage on the VTERM pins
during Powerdown exit.
The XDR DRAM will enter Active state after an interval of
t
PDN-EXIT
has elapsed from the end of the SBW transaction
(this is the parameter that should be used for calculating the
power dissipation of the XDR DRAM).
The first request packet may be issued after an interval of
t
PDN-CMD
has elapsed from the end of the SBW transaction,
and must contain a “REFA” command in a ROWP packet
. In this
example, this packet is denoted with the command “REFA 1”.
No other request packets should be issued during this t
PDN-
CMD
interval.
All “n” banks (in the example, n=2
3
)
must be refreshed using
the current value of the REFr registers. The “nth” refresh
transaction will use a “REFI” command to increment the
REFr register (instead of a “REFR” command). This ensures
that no matter what value has been left in the REFB register,
no row of any bank will be skipped when normal refresh is
restarted in Active state. There may be some banks at the cur-
rent row value in the REFr registers that are refreshed twice
during the Powerdown exit process.
Note that during the Powerdown state an internal time source
keeps the device refreshed. However, during the t
PDN-CMD
interval, no internal refresh operations are performed. As a
result, an additional burst of refresh transactions must be
issued after the burst of “n” transactions described above.
This second burst consists of “m” refresh transactions:
m = ceiling[2
3
*2
12
*t
PDN-CMD
/t
REF
]
Where “2
12
” is the number of rows per bank, and “2
3
” is the
number of banks. Every “nth” refresh transaction (where
n=2
3
) will use a “REFI” command (to increment the REFr
register) instead of a “REFA” command.
相關(guān)PDF資料
PDF描述
EDX5116ABSE-4C-E 512M bits XDR DRAM (32M words ?16 bits)
EDX5116ADSE 512M bits XDR⑩ DRAM
EDX5116ADSE-3B-E 512M bits XDR⑩ DRAM
EDX5116ADSE-3C-E 512M bits XDR⑩ DRAM
EDX5116ADSE-4D-E 512M bits XDR⑩ DRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDX5116ABSE-4C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ACSE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
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