參數(shù)資料
型號(hào)： EDX5116ABSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： LEAD FREE, FBGA-104
文件頁(yè)數(shù)： 24/78頁(yè)
文件大?。?/td> 3611K
代理商： EDX5116ABSE-3C-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
24
EDX5116ABSE
Read Transactions
Figure 10 shows four examples of memory read transactions.
A transaction is one or more request packets (and the associ-
ated data packets) needed to perform a memory access. The
state of the memory core and the address of the memory
access determine how many request packets are needed to per-
form the access.
The first timing diagram shows a page-hit read transaction. In
this case, the selected bank is already open (a row is already
present in the sense amp array for the bank). In addition, the
selected row for the memory access matches the address of the
row already sensed (a page hit). This comparison must be done
in the memory controller. In this example, the access is made
to row Ra of bank Ba.
In this case, read data may be directly read from the sense amp
array for the bank, and no row operations (activate or pre-
charge) are needed. A COL packet with RD command to col-
umn Ca1 of bank Ba is presented on edge T
0
, and a second
COL packet with RD command to column Ca2 of bank Ba is
presented on edge T
2
. Two read data packets Q(a1) and Q(a2)
follow these COL packets after the read data delay t
CAC
. The
two COL packets are separated by the column-cycle time t
CC
.
This is also the length of each read data packet.
The second timing diagram shows an example of a page-miss
read transaction. In this case, the selected bank is already open
(a row is already present in the sense amp array for the bank).
However, the selected row for the memory access does not
match the address of the row already sensed (a page miss). This
comparison must be done in the memory controller. In this
example, the access is made to row Ra of bank Ba, and the
bank contains a row other than Ra.
In this case, read data may not be directly read from the sense
amp array for the bank. It is necessary to close the present row
(precharge) and access the requested row (activate). A pre-
charge command (PRE to bank Ba) is presented on edge T
0
.
An activate command (ACT to row Ra of bank Ba) is pre-
sented on edge T
6
a time t
RP
later. A COL packet with RD
command to column Ca1 of bank Ba is presented on edge T
11
a time t
RCD-R
later. A second COL packet with RD command
to column Ca2 of bank Ba is presented on edge T
13
. Two read
data packets Q(a1) and Q(a2) follow these COL packets after
the read data delay t
CAC
. The two COL packets are separated
by the column-cycle time t
CC
. This is also the length of each
read data packet.
The third timing diagram shows an example of a page-empty
write transaction. In this case, the selected bank is already
closed (no row is present in the sense amp array for the bank).
No row comparison is necessary for this case; however, the
memory controller must still remember that bank Ba has been
left closed. In this example, the access is made to row Ra of
bank Ba.
In this case, read data may not be directly read from the sense
amp array for the bank. It is necessary to access the requested
row (activate). An activate command (ACT to row Ra of bank
Ba) is presented on edge T
0
. A COL packet with RD com-
mand to column Ca1 of bank Ba is presented on edge T
5
a
time t
RCD-R
later. A second COL packet with RD command to
column Ca2 of bank Ba is presented on edge T
7
. Two read data
packets Q(a1) and Q(a2) follow these COL packets after the
read data delay t
CAC
. The two COL packets are separated by
the column-cycle time t
CC
. This is also the length of each read
data packet. After the final read command, it may be necessary
to close the present row (precharge). A precharge command —
PRE to bank Ba — is presented on edge T
10
a time t
RDP
after
the last COL packet with a RD command. Whether the bank
is closed or left open depends on the memory controller and
its page policy.
The fourth timing diagram shows another example of a page-
empty read transaction. This is similar to the previous example
except that it uses one read command instead of two read com-
mands. In this case, the core parameter t
RAS
may also be a con-
straint upon when the precharge command may be issued.
The t
RAS
measures the minimum time between an activate
command and a precharge command to a bank. This time
interval is also constrained by the sum t
RCD-R
+ t
RDP
and must
be set to whichever is larger. These two constraints (t
RAS
and
t
RCD-R
+ t
RDP
) will be a function of the memory device’s speed
bin and the data transfer length (the number of read com-
mands issued between the activate and precharge commands).
In this example, the t
RAS
is greater than the sum t
RCD-R
+ t
RDP
by the amount
t
RDP
.
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EDX5116ABSE-4C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
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EDX5116ACSE-3B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
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