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參數(shù)資料
| 型號： | EDX5116ABSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | LEAD FREE, FBGA-104 |
| 文件頁數(shù)： | 34/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE-3C-E |
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Preliminary Data Sheet E0643E30 (Ver. 3.0)
34
EDX5116ABSE
Register Summary
Figure 17 through Figure 33 show the control registers in the
memory component. The control registers are responsible for
configuring the component’s operating mode, for managing
power state transitions, for managing refresh, and for manag-
ing calibration operations.
A control register may contain up to eight bits. Each figure
shows defined bits in white and reserved bits in gray. Reserved
bits must be written as 0 and must be ignored when read.
Write-only fields must be ignored when read
Each figure displays the following register information:
1.
2.
3.
4.
5.
6.
register name
register mnemonic
register address (SADR[7:0] value needed to access it)
read-only, write-only or read-write
initialization state
description of each defined register field
Figure 17 shows the Serial Identification register. This register
contains the SID[5:0] (serial identification field). This field
contains the serial identification value for the device. The value
is compared to the SID[5:0] field of a serial transaction to
determine if the serial transaction is directed to this device. The
serial identification value is set during the initialization
sequence.
Figure 18 shows the Configuration Register. It contains three
fields. The first is the WIDTH field. This field allows the num-
ber of DQ/DQN pins used for memory read and write
accesses to be adjusted. The SLE field enables data to be writ-
ten into the memory through the serial interface using the
WDSL register.
Figure 19 shows the Power Management Register. It contains
two fields. The first is the PX field. When this field is written
with a 1, the memory component transitions from powerdown
to active state. It is usually unnecessary to write a 0 into this
field; this is done automatically by the PDN command in a
COLX packet. The PST field indicates the current power state
of the memory component.
Figure 20 shows the Write Data Serial Load Register. It permits
data to be written into memory via the Serial Interface.
Figure 23 shows the Refresh Bank Control Register. It contains
two fields: BANK and MBR. The BANK field is read-write
and contains the bank address used by self-refresh during the
powerdown state. The MBR field controls how many banks are
refreshed during each refresh operation. Figure 24, Figure 25,
and Figure 26 show different fields of the Refresh Row Regis-
ter (high, middle, and low). This read-write field contains the
row address used by self- and auto-refresh. See “Refresh Trans-
actions” on page 40 for more details.
Figure 28 and Figure 29 show the Current Calibration 0 and 1
registers. They contain the CCVALUE0 and CCVALUE1
fields, respectively. These are read-write fields which control
the amount of IOL current driven by the DQ and DQN pins
during a read transaction. The Current Calibration 0 Register
controls the even-numbered DQ and DQN pins, and the Cur-
rent Calibration 1 controls the odd-numbered DQ and DQN
pins.
Figure 32 shows the test registers. It is used during device test-
ing. It is not to be read or written during normal operation.
Figure 33 shows the DLY register. This is used to set the value
of t
CAC
and t
CWD
used by the component. See “Timing
Parameters” on page 62
Figure 17
S erial Identific ation (S ID) Register
7
6
5
4
3
2
1
0
Read-only register
SID[7:0] resets to 00000000
2
SID[5:0]
reserved
SID[5:0] - Serial Identification field.
This field contains the serial identification value for the device.
The value is compared to the SID[5:0] field of a serial transaction
to determine if the serial transaction is directed to this device.
The serial identification value is set during the initialization
sequence.
Serial Identification Register
SADR[7:0]: 00000001
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ADSE | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ACSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
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