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參數(shù)資料
| 型號： | EDX5116ABSE-3C-E |
| 廠商： | ELPIDA MEMORY INC |
| 元件分類： | DRAM |
| 英文描述： | 512M bits XDR DRAM (32M words ?16 bits) |
| 中文描述： | 32M X 16 RAMBUS, PBGA104 |
| 封裝： | LEAD FREE, FBGA-104 |
| 文件頁數(shù)： | 12/78頁 |
| 文件大?。?/td> | 3611K |
| 代理商： | EDX5116ABSE-3C-E |
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Preliminary Data Sheet E0643E30 (Ver. 3.0)
12
EDX5116ABSE
Request Field Encoding
Operation-code fields
are encoded within different packet
types to specify commands. Table 3 through Table 6 provides
packet type and encoding summaries.
Table 3 shows the OP field encoding for the five packet types.
The COLM and ROWA packets each specify a single com-
mand: ACT and WRM. The COL, COLX, and ROWP packets
each use additional fields to specify multiple commands: WRX,
XOP, and POP/ROP, respectively. The COLM packet specifies
the masked write command WRM. This is like the WR
unmasked write command, except that a mask field M7..0 indi-
cates whether each byte of the write data packet is written or
not written. The ROWA packet specifies the row activate com-
mand ACT. The COL packet uses the WRX field to specify the
column read and column write (unmasked) commands.
Encoding of the ROP field in the ROWP packet is shown in
Table 4. The first encoding specifies a NOPR (no operation)
command. The REFP command uses the RA field to select a
bank to be precharged. The REFA and REFI commands use
the RA field and REFH/M/L registers to select a bank and
row to be activated for refresh. The REFI command also
increments the REFH/M/L register. The REFP, REFA, and
REFI commands may also be delayed by up to 3*t
CYCLE
using
the RA[7:6] field. The LRR0, LRR1, and LRR2 commands
load the REFH/M/L registers from the RA[7:0] field.
The REFH/M/L registers are also referred to as the REFr reg-
isters. Note that only the bits that are needed for specifying the
refresh row (12 bits in all) are implemented in the REFr regis-
ters
—
the rest are reserved. Note also that the RA2..0 field that
Table 3
OP Field Encoding Summary
OP [3:0]
Packet
Command
Description
0000
-
NOP
No operation.
0001
COL
RD
Column read (WRX=0). Column C9..4 of sense amp in bank BC2..0 is read to DQ bus after DELC*t
CYCLE
.
WR
Column write (WRX=1). Write DQ bus to column C9..4 of sense amp in bank BC2..0 after DELC*t
CYCLE
.
0010
COLX
CALy
XOP3..0 specifies a calibrate or powerdown command — see Table 6 on page 13.
0011
ROWP
PREx
POP2..0 specifies a row precharge command — see Table 5 on page 13.
REFy,LRRr
ROP2..0 specifies a row refresh command or load REFr register command — see Table 4 on page 12.
01xx
ROWA
ACT
Row activate command. Row R11..0 of bank BA2..0 is placed into the sense amp of the bank after DELA*t
CYCLE
.
1xxx
COLM
WRM
Column write command (masked) — mask M7..0 specifies which bytes are written.
Table 4
ROP Field Encoding Summary
ROP[2:0]
Command
Description
000
NOPR
No operation
001
REFP
Refresh precharge command. Bank RA2..0 is precharged.
This command is delayed by {0,1,2,3}*t
CYCLE
(the value is given by the expression (2*RA[7]+RA[6]).
010
REFA
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp.
This command is delayed by {0,1,2,3}*t
CYCLE
(the value is given by the expression (2*RA[7]+RA[6]).
011
REFI
Refresh activate command. Row R[11:0] (from REFH/M/L register) of bank RA2..0 is placed into sense amp.
This command is delayed by {0,1,2,3}*t
CYCLE
(the value is given by the expression (2*RA[7]+RA[6]).
R[11:0] field of REFH/M/L register is incremented after the activate command has completed.
100
LRR0
Load Refresh Low Row register (REFL). RA[7:0] is stored in R[7:0] field.
101
LRR1
Load Refresh Middle Row register (REFM). RA[3:0] is stored in R[11:8] field.
110
LRR2
Load Refresh High Row register — not used with this device.
111
-
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EDX5116ABSE-4C-E | 512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ADSE | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3B-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-3C-E | 512M bits XDR⑩ DRAM |
| EDX5116ADSE-4D-E | 512M bits XDR⑩ DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EDX5116ABSE-4C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits) |
| EDX5116ACSE | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3A-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3B-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
| EDX5116ACSE-3C-E | 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM |
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