參數(shù)資料
型號(hào)： EDX5116ABSE-3C-E
廠商： ELPIDA MEMORY INC
元件分類： DRAM
英文描述： 512M bits XDR DRAM (32M words ?16 bits)
中文描述： 32M X 16 RAMBUS, PBGA104
封裝： LEAD FREE, FBGA-104
文件頁(yè)數(shù)： 59/78頁(yè)
文件大?。?/td> 3611K
代理商： EDX5116ABSE-3C-E
Preliminary Data Sheet E0643E30 (Ver. 3.0)
59
EDX5116ABSE
Timing Conditions
Table 13 summarizes all timing conditions that may be applied
to the memory component. The first section of parameters is
concerned with parameters for the clock signals. The second
section of parameters is concerned with parameters for the
request signals. The third section of parameters is concerned
with parameters for the write data signals. The fourth section
of parameters is concerned with parameters for the serial inter-
face signals. The fifth section is concerned with all other
parameters, including those for refresh, calibration, power state
transitions, and initialization.
Table 13
Timing Conditions
Symbol
Parameter and Other Conditions
Minimum
Maximum
Units
Figure(s)
t
CYCLE
or t
CYC,CFM
CFM RSL clock - cycle time -4000
-3200
-2400
2.000
2.500
3.333
3.830
3.830
3.830
ns
ns
ns
Figure 48
t
R,CFM
, t
F,CFM
CFM/CFMN input - rise and fall time - use minimum for test.
0.080
0.200
t
CYCLE
Figure 48
t
H,CFM
, t
L,CFM
CFM/CFMN input - high and low times
40%
60%
t
CYCLE
Figure 48
t
R,RQ
, t
F,RQ
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
0.080
0.260
t
CYCLE
Figure 49
t
S,RQ
, t
H,RQ
RSL RQ input to sample points @ 2.500 ns
>
t
CYCLE
≥
2.000 ns
(set/hold) @ 3.333 ns
>
t
CYCLE
≥
2.500 ns
@ 3.830 ns
≥
t
CYCLE
≥
3.333 ns
0.170
0.200
0.275
-
-
-
ns
ns
ns
Figure 49
t
IR,DQ
, t
IF,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
0.020
0.074
t
CYCLE
Figure 50
t
S,DQ
, t
H,DQ
DRSL DQ input to sample points @ 2.500 ns
>
t
CYCLE
≥
2.000 ns
(set/hold) @ 3.333 ns
>
t
CYCLE
≥
2.500 ns
@ 3.830 ns
≥
t
CYCLE
≥
3.333 ns
0.052
0.065
0.080
-
-
-
ns
ns
ns
Figure 50
t
DOFF,DQ
DRSL DQ input delay offset (fixed) to sample points
-0.080
+0.080
t
CYCLE
Figure 50
t
CYC,SCK
Serial Interface SCK input - cycle time
20
-
ns
Figure 52
t
R,SCK,
t
F,SCK
Serial Interface SCK input - rise and fall times
-
5.0
ns
Figure 52
t
H,SCK
, t
L,SCK
Serial Interface SCK input - high and low times
40%
60%
t
CYC,SCK
Figure 52
t
IR,SI,
t
IF,SI
Serial Interface CMD,RST,SDI input - rise and fall times
-
5.0
ns
Figure 52
t
S,SI
,t
H,SI
Serial Interface CMD,SDI input to SCK clock edge - set/hold time
5
-
ns
Figure 52
t
DLY,SI-RQ
Delay from last SCK clock edge for register operation to first CFM edge with
RQ packet. Also, delay from first CFM edge with RQ packet to the first SCK
clock edge for register operation.
10
-
t
CYC,SCK
-
t
REF
Refresh interval. Every row of every bank must be accessed at least once in this
interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
-
16
ms
Figure 34
t
REFA-REFA,AVG
Average refresh command interval. ROWP-REFA or ROWP-REFI commands
must be issued at this average rate. This depends upon t
REF
and the number of
banks and rows: t
REFA-REFA,AVG
= t
REF
/(N
B
*N
R
) = t
REF
/(2
3
*2
12
).
t
REFA-REFA,AVG
= 488
ns
-
N
REFA,BURST
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands
which can be issued consecutively at the minimum command spacing.
-
128
commands
-
t
BURST-REFA
Refresh burst interval. The interval between a burst of N
ROWP-REFA or ROWP-REFI commands and the next ROWP-REFA or
ROWP-REFI command.
40
-
t
CYCLE
-
t
COREINIT
Interval needed for core initialialization after power is applied.
-
1.500
ms
-
t
CALC,
t
CALZ
Current calibration interval
-
100
ms
Figure 35
t
CMD-CALC
, t
CMD-CALZ
,
Delay between packet with any command w/ PRE or REFP command
and CALC/CALZ packet w/ any other command
4
16
-
-
t
CYCLE
Figure 35
t
CALCE
, t
CALZE
Delay between CALC/CALZ packet and CALE packet
12
-
t
CYCLE
Figure 35
相關(guān)PDF資料
PDF描述
EDX5116ABSE-4C-E 512M bits XDR DRAM (32M words ?16 bits)
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EDX5116ADSE-3B-E 512M bits XDR⑩ DRAM
EDX5116ADSE-3C-E 512M bits XDR⑩ DRAM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EDX5116ABSE-4C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR DRAM (32M words ?16 bits)
EDX5116ACSE 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3A-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3B-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
EDX5116ACSE-3C-E 制造商:ELPIDA 制造商全稱:Elpida Memory 功能描述:512M bits XDR? DRAM
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