參數(shù)資料
型號: EDS2532EEBH-9A
廠商: Elpida Memory, Inc.
英文描述: 256M bits SDRAM (8M words x 32 bits)
中文描述: 256M位的SDRAM(800萬字× 32位)
文件頁數(shù): 24/50頁
文件大小: 718K
代理商: EDS2532EEBH-9A
EDS2532EEBH-9A
Preliminary Data Sheet E0617E40 (Ver. 4.0)
24
Power-up sequence
Power-up sequence
The SDRAM should be goes on the following sequence with power up.
The CLK, CKE, /CS, DQM and DQ pins keep low till power stabilizes.
The CLK pin is stabilized within 100 μs after power stabilizes before the following initialization sequence.
The CKE and DQM is driven to high between power stabilizes and the initialization sequence.
This SDRAM has VDD clamp diodes for CLK, CKE, address, /RAS, /CAS, /WE, /CS, DQM and DQ pins. If these
pins go high before power up, the large current flows from these pins to VDD through the diodes.
Initialization sequence
When 200 μs or more has past after the above power-up sequence, all banks must be precharged using the
precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). Set the mode register
set command (MRS) to initialize the mode register. If necessary, issue the extended mode register set command
(EMRS) to change the default value of extended mode register after
l
MRD of the MRS command. We recommend
that by keeping DQM and CKE to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ
bus contention on memory system formed with a number of device.
VDD, VDDQ
Power up sequence
Initialization sequence
100
μ
s
0 V
Low
Low
Low
CKE, DQM
CLK
/CS, DQ
200
μ
s
Power stabilize
Power-up sequence and Initialization sequence
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