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參數(shù)資料
| 型號： | EDS2532EEBH-9A |
| 廠商： | Elpida Memory, Inc. |
| 英文描述： | 256M bits SDRAM (8M words x 32 bits) |
| 中文描述： | 256M位的SDRAM（800萬字× 32位） |
| 文件頁數(shù)： | 22/50頁 |
| 文件大小： | 718K |
| 代理商： | EDS2532EEBH-9A |
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EDS2532EEBH-9A
Preliminary Data Sheet E0617E40 (Ver. 4.0)
22
Mode Register and Extended Mode Register Configuration
Mode Register Set
The mode register is set by the input to the address pins (A0 to A11, BA0 and BA1) during mode register set cycles.
The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A8, A9, A10, A11: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode,
and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column address
specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of
the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the /CAS latency.
A3: (BT): A burst type is specified.
A2, A1, A0: (BL): These pins specify the burst length.
A2 A1
A0
Burst length
BT=0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
4
8
R
R
1
1
1
BT=1
1
1
0
R
1
2
4
8
R
R
R
R
A3
0
1
Sequential
Interleave
Burst type
A6
0
0
0
0
1
A5
0
0
1
1
X
A4 CAS latency
0
1
0
1
X
R
R
2
3
R
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
OPCODE
0
LMODE
BT
BL
A9
0
0
0
0
0
1
1
R
Write mode
Burst read and burst write
R
R
R
A8
0
0
0
0
1
0
1
Burst read and single write
R
F.P.: Full Page
R is Reserved (inhibit)
X: 0 or 1
A11
A10
A10
0
X
X
X
X
X
X
A11
0
X
X
X
X
X
X
BA0
BA1
BA1
BA0
0
X
X
X
0
1
0
1
X
X
X
0
1
1
F.P.
Mode Register Set
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|---|---|
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