參數(shù)資料
型號(hào): DSP56301VF100
廠商: Freescale Semiconductor
文件頁數(shù): 79/124頁
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告: DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝: 60
系列: DSP563xx
類型: 定點(diǎn)
接口: 主機(jī)接口,SSI,SCI
時(shí)鐘速率: 100MHz
非易失內(nèi)存: ROM(9 kB)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 252-BGA
供應(yīng)商設(shè)備封裝: 252-MAPBGA(21x21)
包裝: 托盤
DSP56301 Technical Data, Rev. 10
2-32
Freescale Semiconductor
Specifications
2.5.5.5 Asynchronous Bus Arbitrations Timings
Figure 2-25.
Bus Release Timings Case 2 (BRT Bit in Operating Mode Register Set)
Table 2-17.
Asynchronous Bus Arbitration Timing1,3
No.
Characteristics
Expression
80 MHz
100 MHz2
Unit
Min
Max
Min
Max
250
BB assertion window from BG input deassertion4
2.5
× Tc + 5
25
30
ns
251
Delay from BB assertion to BG assertion4
2
× Tc + 5
25
25
ns
Notes:
1.
Bit 13 in the Operating Mode Register must be set to enter Asynchronous Arbitration mode.
2.
Asynchronous Arbitration mode is recommended for operation at 100 MHz.
3.
If Asynchronous Arbitration mode is active, none of the timings in Table 2-16 is required.
4.
In order to guarantee timings 250, and 251, BG inputs must be asserted to different DSP56300 devices on the same bus in
the non-overlap manner shown in Figure 2-26.
A[0–23]
BB
AA[0–3]
CLKOUT
BR
BG
RD, WR
223
218
219
214
212
213
221
224
Note: Address lines A[0–23] hold their state after a read or write operation. AA[0–3] do not hold their
state after a read or write operation.
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