參數(shù)資料
型號: DSP56301VF100
廠商: Freescale Semiconductor
文件頁數(shù): 59/124頁
文件大?。?/td> 0K
描述: IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告: DSP56301 Discontinuation 12/Nov/2009
標準包裝: 60
系列: DSP563xx
類型: 定點
接口: 主機接口,SSI,SCI
時鐘速率: 100MHz
非易失內(nèi)存: ROM(9 kB)
芯片上RAM: 24kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 100°C
安裝類型: 表面貼裝
封裝/外殼: 252-BGA
供應商設備封裝: 252-MAPBGA(21x21)
包裝: 托盤
DSP56301 Technical Data, Rev. 10
iv
Freescale Semiconductor
External Memory Expansion
Data memory expansion to two 16 M
× 24-bit word memory spaces in 24-Bit mode or two 64 K
× 16-bit memory spaces in 16-Bit Compatibility mode
Program memory expansion to one 16 M
× 24-bit words memory space in 24-Bit mode or 64 K ×
16-bit in 16-Bit Compatibility mode
External memory expansion port
Chip Select Logic for glueless interface to SRAMs
Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Reduced Power Dissipation
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and
mode-dependent)
Packaging
The DSP56301 is available in a 208-pin thin quad flat pack (TQFP) or a 252-pin molded array
process-ball grid array (MAP-BGA) package. Both packages are available in lead-bearing and
lead-free versions.
Target Applications
Examples of target applications include:
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
DSP resource boards
High-speed modem banks
Packet telephony
Product Documentation
The three documents listed in the following table are required for a complete description of the
DSP56301 and are necessary to design properly with the part. Documentation is available from the
following sources. (See the back cover for detailed information.)
A local Freescale distributor
A Freescale semiconductor sales office
A Freescale Literature Distribution Center
The World Wide Web (WWW)
Table 1.
DSP56301 Documentation
Name
Description
Order Number
DSP56300 Family
Manual
Detailed description of the DSP56300 family processor core and
instruction set
DSP56300FM/AD
DSP56301 User’s
Manual
Detailed functional description of the DSP56301 memory
configuration, operation, and register programming
DSP56301UM/D
DSP56301
Technical Data
DSP56301 features list and physical, electrical, timing, and
package specifications
DSP56301
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