參數(shù)資料
型號： DSP56301VF100
廠商： Freescale Semiconductor
文件頁數(shù)： 36/124頁
文件大?。?/td> 0K
描述： IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告： DSP56301 Discontinuation 12/Nov/2009
標準包裝： 60
系列： DSP563xx
類型： 定點
接口： 主機接口，SSI，SCI
時鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 252-BGA
供應(yīng)商設(shè)備封裝： 252-MAPBGA（21x21）
包裝： 托盤
Host Interface (HI32)
DSP56301 Technical Data, Rev. 10
Freescale Semiconductor
1-15
HCLK
Input
Host Clock
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Host Bus Clock input.
Non-PCI bus
When HI32 is programmed to interface a universal non-PCI bus and the HI
function is selected, this signal must be connected to a pull-up resistor or
directly to VCC.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
HAD[16–31]
HD[8–23]
Input/Output
Tri-stated
Host Address/Data 16–31
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, these signals are lines 16–31 of the Address/Data bus.
Host Data 8–23
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, these signals are lines 8–23 of the Data bus.
Port B
When the HI32 is configured as GPIO through the DCTR, these signals are
internally disconnected.
These inputs are 5 V tolerant.
HRST
Input
Tri-stated
Hardware Reset
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected, this is the Hardware Reset input.
Hardware Reset
When HI32 is programmed to interface with a universal, non-PCI bus and the
HI function is selected, this is the Hardware Reset Schmitt-trigger signal.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
HINTA
Output, open
drain
Tri-stated
Host Interrupt A
When the HI function is selected, this signal is the Interrupt A open-drain
output.
Port B
When the HI32 is configured as GPIO through the DCTR, this signal is
internally disconnected.
This input is 5 V tolerant.
PVCL
Input
PCI Voltage Clamp
When the HI32 is programmed to interface with a PCI bus and the HI function
is selected and the PCI bus uses a 3 V signal environment, connect this pin to
VCC (3.3 V) to enable the high voltage clamping required by the PCI
specifications. In all other cases, including a 5 V PCI signal environment, leave
the input unconnected.
Table 1-11.
Host Interface (Continued)
Signal Name
Type
State During
Reset
Signal Description
相關(guān)PDF資料
PDF描述
DSP56303VL100B1 IC DSP 24BIT 100MHZ 196-BGA
DSP56311VF150B1 IC DSP 24BIT 150MHZ 196-BGA
DSP56321VF200R2 IC DSP 24BIT 200MHZ 196-BGA
DSP56852VFE IC DSP 16BIT 120MHZ 81-MAPBGA
DSP56854FGE IC DSP 16BIT 120MHZ 128-LQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56301VF80 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC MAP DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
DSP56301VF80B1 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DSP56301VF80B1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT
DSP56301VL100 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Digital Signal Processor
DSP56301VL80 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Digital Signal Processor
DSP56302 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DSP56301 Digital Signal Processor
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*