參數(shù)資料
型號(hào)： DSP56301VF100
廠商： Freescale Semiconductor
文件頁數(shù)： 40/124頁
文件大小： 0K
描述： IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告： DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝： 60
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 252-BGA
供應(yīng)商設(shè)備封裝： 252-MAPBGA（21x21）
包裝： 托盤
DSP56301 Technical Data, Rev. 10
1-18
Freescale Semiconductor
Signals/Connections
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
Table 1-13.
Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal Name
Type
State During
Reset
Signal Description
SC10
PD0
Input or Output
Input
Serial Control 0
Selection of Synchronous or Asynchronous mode determines function. For
Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input).
For Synchronous mode, this signal is either Transmitter 1 output or Serial I/O
Flag 0.
Port D 0
The default configuration following reset is GPIO. For PD0, signal direction is
controlled through the Port Directions Register (PRR1). The signal can be
configured as an ESSI signal SC10 through the Port Control Register (PCR1).
This input is 5 V tolerant.
SC11
PD1
Input/Output
Input or Output
Input
Serial Control 1
Selection of Synchronous or Asynchronous mode determines function. For
Asynchronous mode, this signal is the receiver frame sync I/O. For
Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag
1.
Port D 1
The default configuration following reset is GPIO. For PD1, signal direction is
controlled through PRR1. The signal can be configured as an ESSI signal
SC11 through PCR1.
This input is 5 V tolerant.
SC12
PD2
Input/Output
Input or Output
Input
Serial Control Signal 2
Frame sync for both the transmitter and receiver in Synchronous mode, for the
transmitter only in Asynchronous mode. When configured as an output, this
signal is the internally generated frame sync signal. When configured as an
input, this signal receives an external frame sync signal for the transmitter (and
the receiver in Synchronous operation).
Port D 2
The default configuration following reset is GPIO. For PD2, signal direction is
controlled through PRR1. The signal can be configured as an ESSI signal
SC12 through PCR1.
This input is 5 V tolerant.
SCK1
PD3
Input/Output
Input or Output
Input
Serial Clock
Provides the serial bit rate clock for the ESSI interface. Clock input or output
can be used by the transmitter and receiver in Synchronous modes, by the
transmitter only in Asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half
of the serial clock.
Port D 3
The default configuration following reset is GPIO. For PD3, signal direction is
controlled through PRR1. The signal can be configured as an ESSI signal
SCK1 through PCR1.
This input is 5 V tolerant.
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