參數(shù)資料
型號(hào)： DSP56301VF100
廠商： Freescale Semiconductor
文件頁數(shù)： 51/124頁
文件大小： 0K
描述： IC DSP 24BIT FIXED-POINT 252-BGA
產(chǎn)品變化通告： DSP56301 Discontinuation 12/Nov/2009
標(biāo)準(zhǔn)包裝： 60
系列： DSP563xx
類型： 定點(diǎn)
接口： 主機(jī)接口，SSI，SCI
時(shí)鐘速率： 100MHz
非易失內(nèi)存： ROM（9 kB）
芯片上RAM： 24kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 100°C
安裝類型： 表面貼裝
封裝/外殼： 252-BGA
供應(yīng)商設(shè)備封裝： 252-MAPBGA（21x21）
包裝： 托盤
DSP56301 Technical Data, Rev. 10
2-6
Freescale Semiconductor
Specifications
2.5.3
Phase Lock Loop (PLL) Characteristics
Table 2-5.
Clock Operation
No.
Characteristics
Symbol
80 MHz
100 MHz
Min
Max
Min
Max
1
Frequency of EXTAL (EXTAL Pin Frequency)
The rise and fall time of this external clock should be 3 ns maximum.
Ef
0
80.0 MHz
0
100.0 MHz
2
EXTAL input high1, 2
With PLL disabled (46.7%–53.3% duty cycle6)
With PLL enabled (42.5%–57.5% duty cycle6)
ETH
5.84 ns
5.31 ns
∞
157.0
μs
4.67 ns
4.25 ns
∞
157.0
μs
3
EXTAL input low1, 2
With PLL disabled (46.7%–53.3% duty cycle6)
With PLL enabled (42.5%–57.5% duty cycle6)
ETL
5.84 ns
5.31 ns
∞
157.0
μs
4.67 ns
4.25 ns
∞
157.0
μs
4
EXTAL cycle time2
With PLL disabled
With PLL enabled
ETC
12.50 ns
∞
273.1
μs
10.00 ns
∞
273.1
μs
5
CLKOUT change from EXTAL fall with PLL disabled
4.3 ns
11.0 ns
4.3 ns
11.0 ns
6
a. CLKOUT rising edge from EXTAL rising edge with PLL enabled (MF
= 1 or 2 or 4, PDF = 1, Ef > 15 MHz)3,5
b. CLKOUT falling edge from EXTAL falling edge with PLL enabled (MF
≤ 4, PDF ≠ 1, Ef / PDF > 15 MHz)3,5
0.0 ns
1.8 ns
0.0 ns
1.8 ns
7
Instruction cycle time = ICYC = TC
4
(see Table 2-4) (46.7%–53.3% duty cycle)
With PLL disabled
With PLL enabled
ICYC
25.0 ns
12.50 ns
∞
8.53
μs
20.0 ns
10.00 ns
∞
8.53
μs
Notes:
1.
Measured at 50 percent of the input transition
2.
The maximum value for PLL enabled is given for minimum VCO frequency (see Table 2-6) and maximum MF.
3.
Periodically sampled and not 100 percent tested
4.
The maximum value for PLL enabled is given for minimum VCO frequency and maximum DF.
5.
The skew is not guaranteed for any other MF value.
6.
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time
required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock
frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time
requirements are met.
Table 2-6.
PLL Characteristics
Characteristics
80 MHz
100 MHz
Unit
Min
Max
Min
Max
Voltage Controlled Oscillator (VCO) frequency when PLL
enabled (MF
× Ef × 2/PDF)
30
160
30
200
MHz
PLL external capacitor (PCAP pin to VCCP) (CPCAP
)
@ MF
≤ 4
@ MF > 4
(MF
× 580)
100
MF
× 830
(MF
× 780)
140
MF
× 1470
(MF
× 580) 100
MF
× 830
(MF
× 780) 140
MF
× 1470
pF
Note:
CPCAP is the value of the PLL capacitor (connected between the PCAP pin and VCCP). The recommended value in pF for CPCAP
can be computed from one of the following equations:
(680
× MF) – 120, for MF ≤ 4, or
1100
× MF, for MF > 4.
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